/ uboot-201106-tiny6410-nand
项目语言:C
权限:read-only(如需更高权限请先加入项目)
uboot-201106-tiny6410-nand/
Index: README.LED_display
===================================================================
--- README.LED_display (revision 0)
+++ README.LED_display (revision 2)
@@ -0,0 +1,26 @@
+LED display internal API
+=======================================
+This README describes the LED display API.
+The API is defined by the include file include/led-display.h
+The first step in to define CONFIG_CMD_DISPLAY in the board config file.
+Then you need to provide the following functions to access LED display:
+void display_set(int cmd);
+This function should control the state of the LED display. Argument is
+an ORed combination of the following values:
+ DISPLAY_CLEAR -- clear the display
+ DISPLAY_HOME -- set the position to the beginning of display
+int display_putc(char c);
+This function should display it's parameter on the LED display in the
+current position. Returns the displayed character on success or -1 in
+case of failure.
+With this functions defined 'display' command will display it's
+arguments on the LED display (or clear the display if called without
+arguments).
Property changes on: README.LED_display
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.simpc8313
===================================================================
--- README.simpc8313 (revision 0)
+++ README.simpc8313 (revision 2)
@@ -0,0 +1,80 @@
+Sheldon Instruments SIMPC8313 Board
+-----------------------------------------
+1. Board Switches and Jumpers
+ S2 is used to set CFG_RESET_SOURCE.
+ To boot the image in Large page NAND flash, use these DIP
+ switch settings for S2:
+ +----------+ ON
+ | * * **** |
+ +----------+
+ To boot the image in Small page NAND flash, use these DIP
+ switch settings for S2:
+ +----------+ ON
+ | *** **** |
+ +----------+
+ (where the '*' indicates the position of the tab of the switch.)
+2. Memory Map
+ The memory map looks like this:
+ 0xx1fff_ffff DDR
+ 0xx8fff_ffff PCI MEM
+ 0xx9fff_ffff PCI_MMIO
+ 0xe000_f_ffff IMMR
+ 0xe200_f_ffff PCI IO
+ 0xe280_0_7fff NAND FLASH (CS0) 32K
+ 0xe280_1_ffff NAND FLASH (CS0) 128K
+ 0xff00_0000 0xff00_7fff FPGA (CS1)
+3. Compilation
+ Assuming you're using BASH (or similar) as your shell:
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make SIMPC8313_LP_config
+ (or make SIMPC8313_SP_config, depending on the page size
+ of your NAND flash)
+4. Downloading and Flashing Images
+4.1 Reflash U-boot Image using U-boot
+ =&run update_uboot
+ You may want to try
+ =&tftp $loadaddr $uboot
+ first, to make sure that the TFTP load will succeed before it
+ goes ahead and wipes out your current firmware.
And of course,
+ if the new u-boot doesn't boot, you can plug the board into
+ your PCI slot and with the supplied driver and sample app
+ you can reburn a working u-boot.
+4.2 Downloading and Booting Linux Kernel
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, fdtfile, and bootfile).
+ =&tftp $loadaddr uImage
+ =&nand write $loadaddr kernel $filesize
+ =&tftp $loadaddr $fdtfile
+ =&nand write $loadaddr 7e
+ The console baudrate for SIMPC8313 is 115200bps.
Property changes on: README.simpc8313
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.SBC8560
===================================================================
--- README.SBC8560 (revision 0)
+++ README.SBC8560 (revision 2)
@@ -0,0 +1,57 @@
+The port was tested on Wind River System Sbc8560 board
+&&. U-Boot was installed on the flash memory of the
+CPU card (no the SODIMM).
+NOTE: Please configure uboot compile to the proper PCI frequency and
+setup the appropriate DIP switch settings.
+SBC8560 board:
+Make sure boards switches are set to their appropriate conditions.
+Refer to the Engineering Reference Guide ERG-. Of particular
+importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
+select the on-board FLASH device (Intel 28F128Jx); 2) The settings
+for the Clock SW9 (33 MHz or 66 MHz).
+ Note: SW9 Settings: 66 MHz
4:1 ratio CCB clocks:SYSCLK
3:1 ration e500 Core:CCB
pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
+ Note: SW9 Settings: 33 MHz
8:1 ratio CCB clocks:SYSCLK
3:1 ration e500 Core:CCB
pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
+Flashing the FLASH device with the &Wind River ICE&:
+1) Properly connect and configure the Wind River ICE to the target
JTAG port. This includes running the SBC8560 register script. Make
sure target memory can be read and written.
+2) Build the u-boot image:
+ make distclean
+ make SBC8560_66_config or SBC8560_33_config
+ make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
Note: reference is made to the ELDK3.0 compiler. Further, it seems
the ppc_8xx compiler is required for the 85xx (no 85xx
designated compiler in ELDK3.0)
+3) Convert the uboot (.elf) file to a uboot.bin file (using
visionClick converter). The bin file should be converted from
fffc0000 to ffffffff
+4) Setup the Flash Utility (tools menu) for:
Do a &dc clr& [visionClick] to load the default register settings
Determine the clock speed of the PCI bus and set SW9 accordingly
+ Note: the speed of the PCI bus defaults to the slowest PCI card
PlayBack the &default& register file for the SBC8560
Select the uboot.bin file with zero bias
Select the initialize Target prior to programming
Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
Select the erase base address from FFFC0000 to FFFFFFFF
Select the start address from 0 with size of 4000
+5) Erase and Program
Property changes on: README.SBC8560
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.mpc8313erdb
===================================================================
--- README.mpc8313erdb (revision 0)
+++ README.mpc8313erdb (revision 2)
@@ -0,0 +1,111 @@
+Freescale MPC8313ERDB Board
+-----------------------------------------
+1. Board Switches and Jumpers
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+ +------+ +------+
| | **** |
+ | **** | |
+ +------+ ON +------+ ON
+ (where the '*' indicates the position of the tab of the switch.)
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+ +------+ +------+
+ +------+ ON +------+ ON
+ (where the '*' indicates the position of the tab of the switch.)
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+2. Memory Map
+ The memory map looks like this:
+ 0xx07ff_ffff DDR
+ 0xx8fff_ffff PCI MEM
+ 0xx9fff_ffff PCI_MMIO
+ 0xe000_f_ffff IMMR
+ 0xe200_f_ffff PCI IO
+ 0xe280_0_7fff NAND FLASH (CS1) 32K
+ 0xf000_1_ffff VSC7385 (CS2)
+ 0xfa00_0000 0xfa00_7fff Board Status/
LED Control (CS3)
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0)
+ When booting from NAND, NAND flash is CS0 and NOR flash
+3. Definitions
+3.1 Explanation of NEW definitions in:
+ include/configs/MPC8313ERDB.h
+ CONFIG_MPC83xx
MPC83xx family
+ CONFIG_MPC831x
MPC831x specific
+ CONFIG_MPC8313ERDB MPC8313ERDB board specific
+4. Compilation
+ Assuming you're using BASH (or similar) as your shell:
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8313ERDB_XXX_config
+ (where XXX is:
33 - 33 MHz oscillator, boot from NOR flash
66 - 66 MHz oscillator, boot from NOR flash
NAND_33 - 33 MHz oscillator, boot from NAND flash
NAND_66 - 66 MHz oscillator, boot from NAND flash)
+5. Downloading and Flashing Images
+5.1 Reflash U-boot Image using U-boot
+ NOR flash:
+ =&run tftpflash
+ You may want to try
+ =&tftpboot $loadaddr $uboot
+ first, to make sure that the TFTP load will succeed before it
+ goes ahead and wipes out your current firmware.
And of course,
+ have an alternate means of programming the flash available
+ if the new u-boot doesn't boot.
+ NAND flash:
+ =&tftpboot $loadaddr &filename&
+ =&nand erase 0 0x80000
+ =&nand write $loadaddr 0 0x80000
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+5.2 Downloading and Booting Linux Kernel
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+ =&run nfsboot
+ =&run ramboot
+ The console baudrate for MPC8313ERDB is 115200bps.
Property changes on: README.mpc8313erdb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.mpc8315erdb
===================================================================
--- README.mpc8315erdb (revision 0)
+++ README.mpc8315erdb (revision 2)
@@ -0,0 +1,105 @@
+Freescale MPC8315ERDB Board
+-----------------------------------------
+1. Board Switches and Jumpers
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+ +------+ +------+
| | **** |
+ | **** | |
+ +------+ ON +------+ ON
+ (where the '*' indicates the position of the tab of the switch.)
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+ +------+ +------+
+ +------+ ON +------+ ON
+ (where the '*' indicates the position of the tab of the switch.)
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+2. Memory Map
+ The memory map looks like this:
+ 0xx07ff_ffff DDR
+ 0xx8fff_ffff PCI MEM
+ 0xx9fff_ffff PCI_MMIO
+ 0xe000_f_ffff IMMR
+ 0xe030_f_ffff PCI IO
+ 0xe060_0_7fff NAND FLASH (CS1) 32K
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0)
+ When booting from NAND, NAND flash is CS0 and NOR flash
+3. Definitions
+3.1 Explanation of NEW definitions in:
+ include/configs/MPC8315ERDB.h
+ CONFIG_MPC83xx
MPC83xx family
+ CONFIG_MPC831x
MPC831x specific
+ CONFIG_MPC8315
MPC8315 specific
+ CONFIG_MPC8315ERDB MPC8315ERDB board specific
+4. Compilation
+ Assuming you're using BASH (or similar) as your shell:
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
+ make all
+5. Downloading and Flashing Images
+5.1 Reflash U-boot Image using U-boot
+ NOR flash:
+ tftp 40000 u-boot.bin
+ protect off all
+ erase fe000000 fe1fffff
+ cp.b 40000 fe000000 xxxx
+ protect on all
+ You have to supply the correct byte count with 'xxxx'
+ from the TFTP result log.
+ NAND flash:
+ =&tftpboot $loadaddr &filename&
+ =&nand erase 0 0x80000
+ =&nand write $loadaddr 0 0x80000
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+5.2 Downloading and Booting Linux Kernel
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+ =&run nfsboot
+ =&run ramboot
+ The console baudrate for MPC8315ERDB is 115200bps.
Property changes on: README.mpc8315erdb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.sbc8641d
===================================================================
--- README.sbc8641d (revision 0)
+++ README.sbc8641d (revision 2)
@@ -0,0 +1,28 @@
+Wind River SBC8641D reference board
+===========================
+Created 06/14/2007 Joe Hamman
+Copyright 2007, Embedded Specialties, Inc.
+Copyright 2007 Wind River Systemes, Inc.
+-----------------------------
+1. Building U-Boot
+------------------
+The SBC8641D code is known to build using ELDK 4.1.
$ make sbc8641d_config
Configuring for sbc8641d board...
+2. Switch and Jumper Settings
+-----------------------------
+All Jumpers & Switches are in their default positions.
Please refer to
+the board documentation for details.
Some settings control CPU voltages
+and settings may change with board revisions.
+3. Known limitations
+--------------------
+ The PCI command may hang if no boards are present in either slot.
Property changes on: README.sbc8641d
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.m52277evb
===================================================================
--- README.m52277evb (revision 0)
+++ README.m52277evb (revision 2)
@@ -0,0 +1,231 @@
+Freescale MCF52277EVB ColdFire Development Board
+================================================
+TsiChung Liew(Tsi-Chung.)
+Created Jan 8, 2008
+===========================================
+Changed files:
+==============
+- board/freescale/m52277evb/m52277evb.c Dram setup
+- board/freescale/m52277evb/Makefile Makefile
+- board/freescale/m52277evb/config.mk config make
+- board/freescale/m52277evb/u-boot.lds Linker description
+- arch/m68k/cpu/mcf5227x/cpu.c
cpu specific code
+- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5227x/speed.c
system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5227x/Makefile
+- arch/m68k/cpu/mcf5227x/config.mk config make
+- arch/m68k/cpu/mcf5227x/start.S
start up assembly code
+- doc/README.m52277evb
This readme file
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c
Realtime clock Driver
+- include/asm-m68k/bitops.h
Bit operation function export
+- include/asm-m68k/byteorder.h
Byte order functions
+- include/asm-m68k/crossbar.h
CrossBar structure and definition
+- include/asm-m68k/dspi.h
DSPI structure and definition
+- include/asm-m68k/edma.h
eDMA structure and definition
+- include/asm-m68k/flexbus.h
FlexBus structure and definition
+- include/asm-m68k/fsl_i2c.h
I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h
ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5227x.h mcf5227x specific header file
+- include/asm-m68k/io.h
io functions
+- include/asm-m68k/lcd.h
LCD structure and definition
+- include/asm-m68k/m5227x.h
mcf5227x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h
header file
+- include/asm-m68k/ptrace.h
Exception structure
+- include/asm-m68k/rtc.h
Realtime clock header file
+- include/asm-m68k/ssi.h
SSI structure and definition
+- include/asm-m68k/string.h
String function export
+- include/asm-m68k/timer.h
Timer structure and definition
+- include/asm-m68k/types.h
Data types definition
+- include/asm-m68k/uart.h
Uart structure and definition
+- include/asm-m68k/u-boot.h
u-boot structure
+- include/configs/M52277EVB.h
Board specific configuration file
+- arch/m68k/lib/board.c
board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts
Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c
Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c
Exception init code
+1 MCF52277 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in this coldfire family
+1.2 Configuration settings for M52277EVB Development Board
+CONFIG_MCF5227x
-- define for all MCF5227x CPUs
+CONFIG_M52277
-- define for all Freescale MCF52277 CPUs
+CONFIG_M52277EVB -- define for M52277EVB board
+CONFIG_MCFUART
-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT
-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE
-- define UART baudrate
+CONFIG_MCFRTC
-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE
-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG
-- define to show RTC debug message
+CONFIG_CMD_DATE
-- enable to use date feature in u-boot
+CONFIG_MCFTMR
-- define to use DMA timer
+CONFIG_MCFPIT
-- define to use PIT timer
+CONFIG_FSL_I2C
-- define to use FSL common I2C driver
+CONFIG_HARD_I2C
-- define for I2C hardware support
+CONFIG_SOFT_I2C
-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED
-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE
-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET
-- define for I2C base address offset
+CONFIG_SYS_IMMR
-- define for MBAR offset
+CONFIG_SYS_MBAR
-- define MBAR offset
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot,
+update will be provided at later time
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
0xx3FFFFFFF (1024MB)
0xx7FFFFFFF (1024MB)
0xx8FFFFFFF (256MB)
0xFxFFFFFFFF (256MB)
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
0xx00FFFFFF (16MB)
0xx4FFFFFFF (64MB)
0xx80007FFF (32KB)
0xFCxFC0FFFFF (64KB)
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version)
was used. Download it from:
+/gnu_toolchains/coldfire/download.html
+3.2 Compilation
export CROSS_COMPILE=cross-compile-prefix
cd u-boot-1.x.x
make distclean
make M52277EVB_config
+4. SCREEN DUMP
+==============
+4.1 M52277EVB Development board
(NOTE: May not show exactly the same)
+U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
Freescale MCF52277 (Mask:6c Version:0)
CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
INP CLK 16 Mhz VCO CLK 480 Mhz
+Board: Freescale 52277 EVB
+FLASH: 16 MB
+baudrate=115200
+hostname=M52277EVB
+loadaddr=(0x + 0x10000)
+load=tftp ${loadaddr) ${u-boot}
+upd= run prog
+prog=prot off 0 3era 0 3cp.b ${loadaddr} 0 ${filesize};save
+u-boot=u-boot.bin
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+Environment size: 280/32764 bytes
+-& bdinfo
+flashstart
+flashsize
+flashoffset = 0x
+sramstart
= 0xFC000000
= 115200 bps
- alias for 'help'
- print or set address offset
- print Board Info structure
- boot default, i.e., run 'bootcmd'
- boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
- boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
- Boot vxWorks from an ELF image
- memory compare
+coninfo - print console devices and information
- memory copy
- checksum calculation
- get/set/reset date & time
- enable or disable data cache
- echo args to console
- erase FLASH memory
- print FLASH memory information
- start application at address 'addr'
- print online help
- I2C sub-system
- enable or disable instruction cache
- print header information for application image
- list all images found in flash
+itest - return true/false on integer compare
- load binary file over serial line (kermit mode)
- load S-Record file over serial line
- load binary file over serial line (ymodem mode)
- infinite loop on address range
+ls - list files in a directory (default /)
- memory display
- memory modify (auto-incrementing)
- simple RAM test
- memory write (fill)
- memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
- Perform RESET of the CPU
- run commands in an environment variable
+saveenv - save environment variables to persistent storage
- set environment variables
- delay execution for some time
- run script from memory
+version - print monitor version
Property changes on: README.m52277evb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.m54455evb
===================================================================
--- README.m54455evb (revision 0)
+++ README.m54455evb (revision 2)
@@ -0,0 +1,410 @@
+Freescale MCF54455EVB ColdFire Development Board
+================================================
+TsiChung Liew(Tsi-Chung.)
+Created 4/08/07
+===========================================
+Changed files:
+==============
+- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m54455evb/flash.c
Atmel and INTEL flash support
+- board/freescale/m54455evb/Makefile
+- board/freescale/m54455evb/config.mk config make
+- board/freescale/m54455evb/u-boot.lds Linker description
+- common/cmd_bdinfo.c
Clock frequencies output
+- common/cmd_mii.c
mii support
+- arch/m68k/cpu/mcf5445x/cpu.c
cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c
system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile
+- arch/m68k/cpu/mcf5445x/config.mk config make
+- arch/m68k/cpu/mcf5445x/start.S
start up assembly code
+- doc/README.m54455evb This readme file
+- drivers/net/mcffec.c
ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- include/asm-m68k/bitops.h
Bit operation function export
+- include/asm-m68k/byteorder.h
Byte order functions
+- include/asm-m68k/fec.h
FEC structure and definition
+- include/asm-m68k/fsl_i2c.h
I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h
ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5445x.h mcf5445x specific header file
+- include/asm-m68k/io.h
io functions
+- include/asm-m68k/m5445x.h
mcf5445x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h
header file
+- include/asm-m68k/ptrace.h
Exception structure
+- include/asm-m68k/rtc.h
Realtime clock header file
+- include/asm-m68k/string.h
String function export
+- include/asm-m68k/timer.h
Timer structure and definition
+- include/asm-m68k/types.h
Data types definition
+- include/asm-m68k/uart.h
Uart structure and definition
+- include/asm-m68k/u-boot.h
u-boot structure
+- include/configs/M54455EVB.h Board specific configuration file
+- arch/m68k/lib/board.c
board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts
Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c
Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c
Exception init code
+- rtc/mcfrtc.c
Realtime clock Driver
+1 MCF5445x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+1.2 Configuration settings for M54455EVB Development Board
+CONFIG_MCF5445x
-- define for all MCF5445x CPUs
+CONFIG_M54455
-- define for all Freescale MCF54455 CPUs
+CONFIG_M54455EVB -- define for M54455EVB board
+CONFIG_MCFUART
-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT
-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE
-- define UART baudrate
+CONFIG_MCFRTC
-- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE
-- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG
-- define to show RTC debug message
+CONFIG_CMD_DATE
-- enable to use date feature in u-boot
+CONFIG_MCFFEC
-- define to use common CF FEC driver
+CONFIG_NET_MULTI -- define to use multi FEC in u-boot
+CONFIG_MII
-- enable to use MII driver
+CONFIG_CF_DOMII
-- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX
-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX
-- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1
-- define to enable second FEC in u-boot
+CONFIG_ISO_PARTITION -- enable ISO read/write
+CONFIG_DOS_PARTITION -- enable DOS read/write
+CONFIG_IDE_RESET -- define ide_reset()
+CONFIG_IDE_PREINIT -- define ide_preinit()
+CONFIG_ATAPI
-- define ATAPI support
+CONFIG_LBA48
-- define LBA48 (larger than 120GB) support
+CONFIG_SYS_IDE_MAXBUS
-- define max channel
+CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel
+CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address
+CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset
+CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO
+CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses
+CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers
+CONFIG_SYS_ATA_STRIDE
-- define for Interval between registers
-- define for IO base address
+CONFIG_MCFTMR
-- define to use DMA timer
+CONFIG_MCFPIT
-- define to use PIT timer
+CONFIG_FSL_I2C
-- define to use FSL common I2C driver
+CONFIG_HARD_I2C
-- define for I2C hardware support
+CONFIG_SOFT_I2C
-- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED
-- define for I2C speed
+CONFIG_SYS_I2C_SLAVE
-- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET
-- define for I2C base address offset
+CONFIG_SYS_IMMR
-- define for MBAR offset
+CONFIG_PCI
-- define for PCI support
+CONFIG_PCI_PNP
-- define for Plug n play support
+CONFIG_SYS_PCI_MEM_BUS
-- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS
-- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS
-- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE
-- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS
-- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
+CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
+CONFIG_SYS_MBAR
-- define MBAR offset
+CONFIG_SYS_ATMEL_BOOT
-- To determine the u-boot is booted from Atmel or Intel
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base
+CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
0xx3FFFFFFF (1024MB)
0xx7FFFFFFF (1024MB)
0xx8FFFFFFF (256MB)
0xx9FFFFFFF (256MB)
0xAxBFFFFFFF (512MB)
+ FlexBus: 0xCxDFFFFFFF (512MB)
0xFxFFFFFFFF (256MB)
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Atmel boot:
0xx0007FFFF (512KB)
0xx05FFFFFF (32MB)
+ Intel boot:
0xx01FFFFFF (32MB)
0xx0407FFFF (512KB)
0xx08FFFFFF (16MB)
0xx09FFFFFF (16MB)
0xx4FFFFFFF (256MB)
0xx80007FFF (32KB)
0xFCxFC0FFFFF (64KB)
+3. SWITCH SETTINGS
+==================
+3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+ SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
+ SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
+ SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
+ SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+4. COMPILATION
+==============
+4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
+ was used. Download it from:
+/gnu_toolchains/coldfire/download.html
+4.2 Compilation
export CROSS_COMPILE=cross-compile-prefix
cd u-boot-1.x.x
make distclean
make M54455EVB_config, or
- default to atmel 33Mhz input clock
make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
make M54455EVB_intel_config, or - default to intel 33Mhz input clock
make M54455EVB_i33_config, or - default to intel 33Mhz input clock
make M54455EVB_i66_config, or - default to intel 66Mhz input clock
+5. SCREEN DUMP
+==============
+5.1 M54455EVB Development board
Boot from Atmel (NOTE: May not show exactly the same)
+U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
Freescale MCF54455 (Mask:48 Version:1)
CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
+Board: Freescale M54455 EVB
+FLASH: 16.5 MB
FEC0, FEC1
Bus 0: not available
+bootargs=root=/dev/ram rw
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+hostname=M54455EVB
+netdev=eth0
+loadaddr=
+load=tftp ${loadaddr) ${u-boot}
+upd= run prog
+prog=prot off 0 2era 0 2cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+mtdids=nor0=M54455EVB-1
+mtdparts=M54455EVB-1:16m(user)
+u-boot=u-boot54455.bin
+filesize=292b4
+fileaddr=
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+Environment size: 563/8188 bytes
+-& bdinfo
+flashstart
+flashsize
+flashoffset = 0x
+sramstart
= 0xFC000000
= 133.333 MHz
= 33.333 MHz
= 66.666 MHz
= 33.333 MHz
= 533.333 MHz
= 00:E0:0C:BC:E5:60
= 00:E0:0C:BC:E5:61
= 192.168.1.3
= 115200 bps
- alias for 'help'
- print or set address offset
- print Board Info structure
- boot default, i.e., run 'bootcmd'
- boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
- boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
- Boot vxWorks from an ELF image
- memory compare
+coninfo - print console devices and information
- memory copy
- checksum calculation
- get/set/reset date & time
- enable or disable data cache
+diskboot- boot from IDE device
- echo args to console
- erase FLASH memory
+ext2load- load binary file from a Ext2 filesystem
- list files in a directory (default /)
+fatinfo - print information about filesystem
+fatload - load binary file from a dos filesystem
- list files in a directory (default /)
- print FLASH memory information
+fsinfo - print information about filesystems
+fsload - load binary file from a filesystem image
- start application at address 'addr'
- print online help
- I2C sub-system
- enable or disable instruction cache
- IDE sub-system
- print header information for application image
- list all images found in flash
+itest - return true/false on integer compare
- load binary file over serial line (kermit mode)
- load S-Record file over serial line
- load binary file over serial line (ymodem mode)
- infinite loop on address range
+ls - list files in a directory (default /)
- memory display
- MII utility commands
- memory modify (auto-incrementing)
- simple RAM test
- memory write (fill)
+nfs - boot image via network using NFS protocol
- memory modify (constant address)
- list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
- Perform RESET of the CPU
- run commands in an environment variable
+saveenv - save environment variables to persistent storage
- set environment variables
- delay execution for some time
- run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-&bootm 4000000
+## Booting image at
Image Name:
Linux Kernel Image
15:13:00 UTC
Image Type:
M68K Linux Kernel Image (uncompressed)
Data Size:
2301952 Bytes =
Load Address:
Entry Point:
Verifying Checksum ... OK
+Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0
+erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
+starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
+Built 1 zonelists.
Total pages: 32624
+Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
+ysmap-flash.0:5M(kernel)ro,-(jffs2)
+PID hash table entries: 1024 (order: 10, 4096 bytes)
+Console: colour dummy device 80x25
+Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
+Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
+Memory: 2136k available (1864k kernel code, 2440k data, 88k init)
+Mount-cache hash table entries: 1024
+NET: Registered protocol family 16
+SCSI subsystem initialized
+NET: Registered protocol family 2
+IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
+TCP established hash table entries: 8192 (order: 2, 32768 bytes)
+TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
+TCP: Hash tables configured (established 8192 bind 4096)
+TCP reno registered
+JFFS2 version 2.2. (NAND) (C)
Red Hat, Inc.
+io scheduler noop registered
+io scheduler anticipatory registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00
+ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
+RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
+loop: loaded (max 8 devices)
+FEC ENET Version 0.2
+fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
+eth0: ethernet 00:08:ee:00:e4:19
+physmap platform flash device:
+physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+2 cmdlinepart partitions found on MTD device physmap-flash.0
+Creating 2 MTD partitions on &physmap-flash.0&:
+0xx : &kernel&
+mtd: Giving out device 0 to kernel
+0xx : &jffs2&
+mtd: Giving out device 1 to jffs2
+mice: PS/2 mouse device common for all mice
+i2c /dev entries driver
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+NET: Registered protocol family 15
+VFS: Mounted root (jffs2 filesystem).
+Setting the hostname to freescale
+Mounting filesystems
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
+Starting syslogd and klogd
+Setting up networking on loopback device:
+Setting up networking on eth0:
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+Adding static route for default gateway to 172.27.255.254:
+Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
+Starting inetd:
Property changes on: README.m54455evb
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.imx31
===================================================================
--- README.imx31 (revision 0)
+++ README.imx31 (revision 2)
@@ -0,0 +1,29 @@
+U-Boot for Freescale i.MX31
+This file contains information for the port of U-Boot to the Freescale
+i.MX31 SoC.
+1. CONFIGURATION OPTIONS/SETTINGS
+---------------------------------
+1.1 Configuration of MC13783 SPI bus
+------------------------------------
+ The power management companion chip MC13783 is connected to the
+ i.MX31 via an SPI bus. Use the following configuration options
+ to setup the bus and chip select used for a particular board.
+ CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to.
Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3.
+ CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to.
+1.2 Timer precision
+-------------------
+ CONFIG_MX31_TIMER_HIGH_PRECISION
+ Enable higher precision timer. The low-precision timer
+ (default) provides approximately 4% error, whereas the
+ high-precision timer is about 0.4% accurate. The extra
+ accuracy is achieved at the cost of higher computational
+ overhead, which, in places where time is measured, should
+ not be critical, so, it should be safe to enable this
Property changes on: README.imx31
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.ne2000
===================================================================
--- README.ne2000 (revision 0)
+++ README.ne2000 (revision 2)
@@ -0,0 +1,38 @@
+This driver supports NE2000 compatible cards (those based on DP8390,
+DP83902 and similar). It can be used with PCMCIA/CF cards provided
+that the CCR is correctly initialized.
+The code is based on sources from the Linux kernel (pcnet_cs.c,
+8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2
+wonderful world are GPL, so this is, of course, GPL.
+I developed and tested this driver on a custom PXA255 based system and
+with a billionton CF network card connected to the PCMCIA interface of
+the micro (have a look at README.PXA_CF for the support of this port).
+The options you have to specify in the config file are (with the
+value for my board as an example):
+#define CONFIG_DRIVER_NE2000
+- Enables the driver
+#define CONFIG_DRIVER_NE2000_BASE (0xx300)
+- Address where the board is mapped
+#define CONFIG_DRIVER_NE2000_CCR (0xx3f8)
+- Address of the CCR (card configuration register). It could be found
+by enabling DEBUG in cmd_pcmcia.c. If this is not defined nothing is
+done as far as PCMCIA support is concerned.
+#define CONFIG_DRIVER_NE2000_VAL (0x20)
+- The value to be written in the CCR. It selects among different I/O
+spaces that could be used by the card.
+Christian Pellegrin &&
Property changes on: README.ne2000
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.hwconfig
===================================================================
--- README.hwconfig (revision 0)
+++ README.hwconfig (revision 2)
@@ -0,0 +1,50 @@
+To enable this feature just define CONFIG_HWCONFIG in your board
+config file.
+This implements a simple hwconfig infrastructure: an
+interface for software knobs to control hardware.
+This a is very simple implementation, i.e. it is implemented
+via the `hwconfig' environment variable. Later we could write
+some &hwconfig &enable|disable|list&& commands, ncurses
+interface for Award BIOS-like interface, and frame-buffer
+interface for AMI GUI[1] BIOS-like interface with mouse
+support[2].
+Current implementation details/limitations:
+1. Doesn't support options dependencies and mutual exclusion.
We can implement this by integrating apt-get[3] into Das
U-Boot. But I haven't bothered yet.
+2. Since we don't implement a hwconfig command, i.e. we're working
with the environement directly, there is no way to tell that
toggling a particular option will need a reboot to take
effect. So, for now it's advised to always reboot the
target after modifying the hwconfig variable.
+3. We support hwconfig options with arguments. For example,
set hwconfig &dr_usb:mode=peripheral,phy_type=ulpi&
This selects three hwconfig options:
1. dr_usb - enable Dual-Role USB
2. dr_usb_mode:peripheral - USB in F
3. dr_usb_phy_type:ulpi - USB should work with ULPI PHYs.
+The purpose of this simple implementation is to refine the
+internal API and then we can continue improving the user
+experience by adding more mature interfaces, like a hwconfig
+command with bells and whistles. Or not adding, if we feel
+that the current interface fits people's needs.
+[1] http://en.wikipedia.org/wiki/American_Megatrends
+[2] Regarding ncurses and GUI with mouse support -- I'm just
+[3] The comment regarding apt-get is also a joke, meaning that
dependency tracking could be non-trivial. For example, for
enabling HW feature X we may need to disable Y, and turn Z
into reduced mode (like RMII-only interface for ethernet,
It's quite trivial to implement simple cases though.
Property changes on: README.hwconfig
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.blackfin
===================================================================
--- README.blackfin (revision 0)
+++ README.blackfin (revision 2)
@@ -0,0 +1,46 @@
+Notes for the Blackfin architecture port of Das U-Boot
+ =========
+ ! ABOUT !
+ =========
+&marketing blurb&
+Blackfin Processors embody a new breed of 16/32-bit embedded processor, ideally
+suited for products where a convergence of capabilities are necessary -
+multi-format audio, video, voice
multi-mode baseband and
+ and real-time security.
The Blackfin's
+unique combination of software flexibility and scalability has gained it
+widespread adoption in convergent applications.
+&/marketing blurb&
+The Blackfin processor is wholly developed by Analog Devices Inc.
+ ===========
+ ! SUPPORT !
+ ===========
+All open source code for the Blackfin processors are being handled via our
+collaborative website:
+http://blackfin.uclinux.org/
+In particular, bug reports, feature requests, help etc... for Das U-Boot are
+handled in the Das U-Boot sub project:
+http://blackfin.uclinux.org/gf/project/u-boot
+This website is backed both by an open source community as well as a dedicated
+team from Analog Devices Inc.
+ =============
+ ! TOOLCHAIN !
+ =============
+To compile the Blackfin aspects, you'll need the GNU toolchain configured for
+the Blackfin processor.
You can obtain such a cross-compiler here:
+http://blackfin.uclinux.org/gf/project/toolchain
+ =================
+ ! DOCUMENTATION !
+ =================
+For Blackfin specific documentation, you can visit our dedicated doc wiki:
+http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot
Property changes on: README.blackfin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.ocotea
===================================================================
--- README.ocotea (revision 0)
+++ README.ocotea (revision 2)
@@ -0,0 +1,73 @@
AMCC Ocotea Board
Last Update: March 2, 2004
+=======================================================================
+This file contains some handy info regarding U-Boot and the AMCC
+Ocotea 440gx
evalutation board. See the README.ppc440 for additional
+information.
+SWITCH SETTINGS & JUMPERS
+==========================
+Here's what I've been using successfully. If you feel inclined to
+change things ... please read the docs!
+------------------------
+J41: strapped
+J42: open
+All others are factory default.
+I2C Information
+=====================
+See README.ebony for information.
+===========================
+Untested at the time of writing.
+PPC440GX Ethernet EMACs
+===========================
+All EMAC ports have been tested and are known to work
+with EPS Group 4.
+Special note about the Cicada CIS8201:
+ The CIS8201 Gigabit PHY comes up in GMII mode by default.
+ One must hit an extended register to allow use of RGMII mode.
+ This has been done in the 440gx_enet.c file with a #ifdef/endif
+AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
+The addresses contained in the config header file are from my particular
+board and you _*should*_ change them to reflect your board either in the
+config file and/or in your environment variables.
I found the addresses on
+labels on the bottom side of the board.
+BDI2k or JTAG Debugging
+===========================
+For ease of debugging you can swap the small boot flash and external SRAM
+by changing U46:3 to on.
You can then use the sram as your boot flash by
+loading the sram via the jtag debugger.
Property changes on: README.ocotea
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.JFFS2
===================================================================
--- README.JFFS2 (revision 0)
+++ README.JFFS2 (revision 2)
@@ -0,0 +1,74 @@
+JFFS2 options and usage.
+-----------------------
+JFFS2 in U-Boot is a read only implementation of the file system in
+Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2.
+The module adds three new commands.
- load binary file from a file system image
- print information about file systems
- list files in a directory
- change active partition
+If you boot from a partition which is mounted writable, and you
+update your boot environment by replacing single files on that
+partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning
+the JFFS2 filesystem takes *much* longer with this feature, though.
+Sorting is done while inserting into the fragment list, which is
+more or less a bubble sort. That algorithm is known to be O(n^2),
+thus you should really consider if you can avoid it!
+There is two ways for JFFS2 to find the disk. The default way uses
+the flash_info structure to find the start of a JFFS2 disk (called
+partition in the code) and you can change where the partition is with
+two defines.
+CONFIG_SYS_JFFS2_FIRST_BANK
+ defined the first flash bank to use
+CONFIG_SYS_JFFS2_FIRST_SECTOR
+ defines the first sector to use
+The second way is to define CONFIG_SYS_JFFS_CUSTOM_PART and implement the
+jffs2_part_info(int part_num) function in your board specific files.
+In this mode CONFIG_SYS_JFFS2_FIRST_BANK and CONFIG_SYS_JFFS2_FIRST_SECTOR is not
+The input is a partition number starting with 0.
+Return a pointer to struct part_info or NULL
+Ex jffs2_part_info() for one partition.
+#if defined CONFIG_SYS_JFFS_CUSTOM_PART
+#include &jffs2/jffs2.h&
+static struct part_
+struct part_info*
+jffs2_part_info(int part_num)
+ if(part_num==0){
if(part.usr_priv==(void*)1)
memset(&part, 0, sizeof(part));
part.offset=(char*)0xFF800000;
part.size=;
/* Mark the struct as ready */
part.usr_priv=(void*)1;
+ return 0;
+ Remove the assumption that JFFS can dereference a pointer
+ into the disk. The current code do not work with memory holes
+ or hardware with a sliding window (PCMCIA).
Property changes on: README.JFFS2
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.m5253evbe
===================================================================
--- README.m5253evbe (revision 0)
+++ README.m5253evbe (revision 2)
@@ -0,0 +1,103 @@
+Freescale Amadeus Plus M5253EVBE board
+======================================
+Hayden Fraser(Hayden.)
+Created 06/05/2007
+===========================================
+1. SWITCH SETTINGS
+==================
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ SDR: 0xx00ffffff
+ SRAM0: 0xx20017fff
+ SRAM1: 0xx2000ffff
+ MBAR1: 0xx4fffffff
+ MBAR2: 0xxCfffffff
+ Flash: 0xffe00000-0xffffffff
+3. DEFINITIONS AND COMPILATION
+==============================
+3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
+ CONFIG_MCF52x2
Processor family
+ CONFIG_MCF5253
MCF5253 specific
+ CONFIG_M5253EVBE Amadeus Plus board specific
+ CONFIG_SYS_CLK
Define Amadeus Plus CPU Clock
+ CONFIG_SYS_MBAR
MBAR base address
+ CONFIG_SYS_MBAR2
MBAR2 base address
+3.2 Compilation
+ export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
+ cd u-boot-1-2-x
+ make distclean
+ make M5253EVBE_config
+4. SCREEN DUMP
+==============
+4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
Freescale Coldfire MCF5253 at 62 MHz
+Board: Freescale MCF5253 EVBE
+=& flinfo
+Bank # 1: CFI conformant FLASH (16 x 16)
Size: 2 MB in 35 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
Erase timeout: 16384 ms, write timeout: 1 ms
Sector Start Addresses:
+=& bdinfo
+boot_params = 0x00F62F90
+flashstart
= 0xFFE00000
+flashsize
+flashoffset = 0x
= 19200 bps
+=& printenv
+bootdelay=5
+baudrate=19200
+stdin=serial
+stdout=serial
+stderr=serial
+Environment size: 134/8188 bytes
+=& saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+5. COMPILER
+-----------
+To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
+compiler set (freescale-coldfire-4.1-elf) from
+You can download it from:/gnu_toolchains/coldfire/download.html
+compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
+codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
Property changes on: README.m5253evbe
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.davinci
===================================================================
--- README.davinci (revision 0)
+++ README.davinci (revision 2)
@@ -0,0 +1,141 @@
+This README is about U-Boot support for TI's ARM 926EJS based family of SoCs.
+These SOCs are used for cameras, video security and surveillance, DVR's, etc.
+DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's
+Additionally there are some SOCs meant for the audio market which though have
+an OMAP part number are very similar to the DaVinci series of SOC's
+Additionally, some family members contain a TI DSP and/or graphics
+co processors along with a host of other peripherals.
+Currently the following boards are supported:
+* TI DaVinci DM644x EVM
+* TI DaVinci DM646x EVM
+* TI DaVinci DM355 EVM
+* TI DaVinci DM365 EVM
+* TI DA830 EVM
+* TI DA850 EVM
+* DM355 based Leopard board
+* DM644x based schmoogie board
+* DM644x based sffsdr board
+* DM644x based sonata board
+* TI DaVinci DM644x EVM:
+make davinci_dvevm_config
+* TI DaVinci DM646x EVM:
+make davinci_dm6467evm_config
+* TI DaVinci DM355 EVM:
+make davinci_dm355evm_config
+* TI DaVinci DM365 EVM:
+make davinci_dm365evm_config
+* TI DA830 EVM:
+make da830evm_config
+* TI DA850 EVM:
+make da850evm_config
+* DM355 based Leopard board:
+make davinci_dm355leopard_config
+* DM644x based schmoogie board:
+make davinci_schmoogie_config
+* DM644x based sffsdr board:
+make davinci_sffsdr_config
+* DM644x based sonata board:
+make davinci_sonata_config
+Bootloaders
+===============
+The DaVinci SOC's use 2 bootloaders. The low level initialization
+is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash
+by a programmer. During initial bootup, the ROM Bootloader reads the UBL
+from a storage device and loads it into the IRAM. The UBL then loads the U-Boot
+into the RAM.
+The programmers and UBL are always released as part of any standard TI
+software release associated with an SOC.
+Environment Variables
+=====================
+The DA850 EVM allows the user to specify the maximum cpu clock allowed by the
+silicon, in Hz, via an environment variable &maxcpuclk&.
+The maximum clock rate allowed depends on the silicon populated on the EVM.
+Please make sure you understand the restrictions placed on this clock in the
+device specific datasheet before setting up this variable. This information is
+passed to the Linux kernel using the ATAG_REVISION atag.
+If &maxcpuclk& is not defined, the configuration CONFIG_DA850_EVM_MAX_CPU_CLK
+is used to obtain this information.
+1) TI DaVinci DM355 EVM:
+/docs/prod/folders/print/tms320dm355.html
+/product_info.php?cPath=103&products_id=203&osCsid=c499afb3da19b4e8f1af32
+2) TI DaVinci DM365 EVM:
+/docs/prod/folders/print/tms320dm365.html?247SEM=
+/boards/evmdm365/revc/
+3) DaVinci DM355 based leopard board
+http://designsomething.org/leopardboard/default.aspx
+/product_info.php?cPath=103&products_id=192&osCsid=67cffc57cbb1
+4) TI DaVinci DM6467 EVM:
+/docs/prod/folders/print/tms320dm6467.html
+/boards/evmdm6467/revf/
+5) TI DaVinci DM6446 EVM:
+/docs/prod/folders/print/tms320dm6446.html
+/product_info.php?cPath=103&products_id=222
+6) TI DA830 EVM
+/apps/docs/gencontent.tsp?appId=1&contentId=52385
+/product_info.php?cPath=37&products_id=214
+7) TI DA850 EVM
+/docs/prod/folders/print/omap-l138.html
+/products/development-kits/zoom-omap-l138-evm-development-kit
Property changes on: README.davinci
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.omap3
===================================================================
--- README.omap3 (revision 0)
+++ README.omap3 (revision 2)
@@ -0,0 +1,170 @@
+This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
+family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
+some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D
+graphics processor and various other standard peripherals.
+Currently the following boards are supported:
+* OMAP3530 BeagleBoard [2]
+* Gumstix Overo [3]
+* TI EVM [4]
+* OpenPandora Ltd. Pandora [5]
+* TI/Logic PD Zoom MDK [6]
+* TI/Logic PD Zoom 2 [7]
+* CompuLab Ltd. CM-T35 [8]
+Toolchain
+=========
+While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
+with -march=armv5 to allow more compilers to work. For U-Boot code this has
+no performance impact.
+* BeagleBoard:
+make omap3_beagle_config
+* Gumstix Overo:
+make omap3_overo_config
+* TI EVM:
+make omap3_evm_config
+* Pandora:
+make omap3_pandora_config
+* Zoom MDK:
+make omap3_zoom1_config
+* Zoom 2:
+make omap3_zoom2_config
+* CM-T35:
+make cm_t35_config
+Custom commands
+===============
+To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
+for OMAP3 supports custom user command
+nandecc hw/sw
+To be compatible with NAND drivers using SW ECC (e.g. kernel code)
+nandecc sw
+enables SW ECC calculation. HW ECC enabled with
+nandecc hw
+is typically used to write 2nd stage bootloader (known as 'x-loader') which is
+executed by OMAP3's boot rom and therefore has to be written with HW ECC.
+For all other commands see
+Interfaces
+==========
+To set a bit :
+ if (!omap_request_gpio(N)) {
omap_set_gpio_direction(N, 0);
omap_set_gpio_dataout(N, 1);
+To clear a bit :
+ if (!omap_request_gpio(N)) {
omap_set_gpio_direction(N, 0);
omap_set_gpio_dataout(N, 0);
+To read a bit :
+ if (!omap_request_gpio(N)) {
omap_set_gpio_direction(N, 1);
val = omap_get_gpio_datain(N);
omap_free_gpio(N);
+ if (val)
printf(&GPIO N is set\n&);
printf(&GPIO N is clear\n&);
+Acknowledgements
+================
+OMAP3 U-Boot is based on U-Boot tar ball [9] for BeagleBoard and EVM done by
+several TI employees.
+[1] OMAP3:
+/omap3 (high volume) and
+/omap35x (broad market)
+[2] OMAP3530 BeagleBoard:
+http://beagleboard.org/
+[3] Gumstix Overo:
+http://www.gumstix.net/Overo/
+[4] TI EVM:
+/docs/toolsw/folders/print/tmdxevm3503.html
+[5] OpenPandora Ltd. Pandora:
+http://openpandora.org/
+[6] TI/Logic PD Zoom MDK:
+/products/devkit/ti/zoom_mobile_development_kit
+[7] TI/Logic PD Zoom 2
+/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
+[8] CompuLab Ltd. CM-T35:
+pulab.co.il/t3530/html/t3530-cm-datasheet.htm
+[9] TI OMAP3 U-Boot:
+/files/u-boot_beagle_revb.tar.gz
Property changes on: README.omap3
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.amigaone
===================================================================
--- README.amigaone (revision 0)
+++ README.amigaone (revision 2)
@@ -0,0 +1,12 @@
+AmigaOne U-Boot and the SciTech emulator
+The directory board/MAI/bios_emulator contains the source code
+of the SciTech x86 emulator. This emulator is normally available
+under a BSD license. However, SciTech kindly gave us permission
+to use their emulator in PPCBoot for the AmigaOne. It's available
+in this form only under GPL.
+Thanks to Kendall Bennett and the rest of the team at SciTech.
for their web site
+The GPL license can be found at http://www.gnu.org/licenses/gpl.html
Property changes on: README.amigaone
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.SNTP
===================================================================
--- README.SNTP (revision 0)
+++ README.SNTP (revision 2)
@@ -0,0 +1,17 @@
+To use SNTP support, add define CONFIG_CMD_SNTP to the
+configuration file of the board.
+The &sntp& command gets network time from NTP time server and
+syncronize RTC of the board. This command needs the command line
+parameter of server's IP address or environment variable
+&ntpserverip&. The network time is sent as UTC. So if you want to
+set local time to RTC, set the offset in second from UTC to the
+enviroment variable &time offset&.
+If the DHCP server provides time server's IP or time offset, you
+don't need to set the above environment variables yourself.
+Current limitations of SNTP support:
+1. The roundtrip time is ignored.
+2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will
Property changes on: README.SNTP
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
\ No newline at end of property
Index: README.POST
===================================================================
--- README.POST (revision 0)
+++ README.POST (revision 2)
@@ -0,0 +1,743 @@
+Power-On-Self-Test support in U-Boot
+------------------------------------
+This project is to support Power-On-Self-Test (POST) in U-Boot.
+1. High-level requirements
+The key requirements for this project are as follows:
+1) The project shall develop a flexible framework for implementing
and running Power-On-Self-Test in U-Boot. This framework shall
possess the following features:
o) Extensibility
The framework shall allow adding/removing/replacing POST tests.
Also, standalone POST tests shall be supported.
o) Configurability
The framework shall allow run-time configuration of the lists
of tests running on normal/power-fail booting.
o) Controllability
The framework shall support manual running of the POST tests.
+2) The results of tests shall be saved so that it will be possible to
retrieve them from Linux.
+3) The following POST tests shall be developed for MPC823E-based
o) CPU test
o) Cache test
o) Memory test
o) Ethernet test
o) Serial channels test
o) Watchdog timer test
o) RTC test
o) I2C test
o) SPI test
o) USB test
+4) The LWMON board shall be used for reference.
+2. Design
+This section details the key points of the design for the project.
+The whole project can be divided into two independent tasks:
+enhancing U-Boot/Linux to provide a common framework for running POST
+tests and developing such tests for particular hardware.
+2.1. Hardware-independent POST layer
+A new optional module will be added to U-Boot, which will run POST
+tests and collect their results at boot time. Also, U-Boot will
+support running POST tests manually at any time by executing a
+special command from the system console.
+The list of available POST tests will be configured at U-Boot build
+time. The POST layer will allow the developer to add any custom POST
+tests. All POST tests will be divided into the following groups:
1) Tests running on power-on booting only
This group will contain those tests that run only once on
power-on reset (e.g. watchdog test)
2) Tests running on normal booting only
This group will contain those tests that do not take much
time and can be run on the regular basis (e.g. CPU test)
3) Tests running in special &slow test mode& only
This group will contain POST tests that consume much time
and cannot be run regularly (e.g. strong memory test, I2C test)
4) Manually executed tests
This group will contain those tests that can be run manually.
+If necessary, some tests may belong to several groups simultaneously.
+For example, SDRAM test may run in both normal and &slow test& mode.
+In normal mode, SDRAM test may perform a fast superficial memory test
+only, while running in slow test mode it may perform a full memory
+check-up.
+Also, all tests will be discriminated by the moment they run at.
+Specifically, the following groups will be singled out:
1) Tests running before relocating to RAM
These tests will run immediately after initializing RAM
as to enable modifying it without taking care of its
contents. Basically, this group will contain memory tests
2) Tests running after relocating to RAM
These tests will run immediately before entering the main
loop as to guarantee full hardware initialization.
+The POST layer will also distinguish a special group of tests that
+may cause system rebooting (e.g. watchdog test). For such tests, the
+layer will automatically detect rebooting and will notify the test
+about it.
+2.1.1. POST layer interfaces
+This section details the interfaces between the POST layer and the
+rest of U-Boot.
+The following flags will be defined:
+#define POST_POWERON
0x01 /* test runs on power-on booting */
+#define POST_NORMAL
0x02 /* test runs on normal booting */
+#define POST_SLOWTEST
0x04 /* test is slow, enabled by key press */
+#define POST_POWERTEST
0x08 /* test runs after watchdog reset */
+#define POST_ROM
0x100 /* test runs in ROM */
+#define POST_RAM
0x200 /* test runs in RAM */
+#define POST_MANUAL
0x400 /* test can be executed manually */
+#define POST_REBOOT
0x800 /* test may cause rebooting */
+#define POST_PREREL
/* test runs before relocation */
+The POST layer will export the following interface routines:
o) int post_run(bd_t *bd, char *name, int flags);
This routine will run the test (or the group of tests) specified
by the name and flag arguments. More specifically, if the name
argument is not NULL, the test with this name will be performed,
otherwise all tests running in ROM/RAM (depending on the flag
argument) will be executed. This routine will be called at least
twice with name set to NULL, once from board_init_f() and once
from board_init_r(). The flags argument will also specify the
mode the test is executed in (power-on, normal, power-fail,
o) void post_reloc(ulong offset);
This routine will be called from board_init_r() and will
relocate the POST test table.
o) int post_info(char *name);
This routine will print the list of all POST tests that can be
executed manually if name is NULL, and the description of a
particular test if name is not NULL.
o) int post_log(char *format, ...);
This routine will be called from POST tests to log their
results. Basically, this routine will print the results to
stderr. The format of the arguments and the return value
will be identical to the printf() routine.
+Also, the following board-specific routines will be called from the
+U-Boot common code:
o) int board_power_mode(void)
This routine will return the mode the system is running in
(POST_POWERON, POST_NORMAL or POST_SHUTDOWN).
o) void board_poweroff(void)
This routine will turn off the power supply of the board. It
will be called on power-fail booting after running all POST
o) int post_hotkeys_pressed(gd_t *gd)
This routine will scan the keyboard to detect if a magic key
combination has been pressed, or otherwise detect if the
power-on long-running tests shall be executed or not (&normal&
versus &slow& test mode).
+The list of available POST tests be kept in the post_tests array
+filled at U-Boot build time. The format of entry in this array will
+be as follows:
+struct post_test {
int (*test)(bd_t *bd, int flags);
This field will contain a short name of the test, which will be
used in logs and on listing POST tests (e.g. CPU test).
This field will keep a name for identifying the test on manual
testing (e.g. cpu). For more information, refer to section
&Command line interface&.
This field will contain a detailed description of the test,
which will be printed on user request. For more information, see
section &Command line interface&.
This field will contain a combination of the bit flags described
above, which will specify the mode the test is running in
(power-on, normal, power-fail or manual mode), the moment it
should be run at (before or after relocating to RAM), whether it
can cause system rebooting or not.
This field will contain a pointer to the routine that will
perform the test, which will take 2 arguments. The first
argument will be a pointer to the board info structure, while
the second will be a combination of bit flags specifying the
mode the test is running in (POST_POWERON, POST_NORMAL,
POST_SLOWTEST, POST_MANUAL) and whether the last execution of
the test caused system rebooting (POST_REBOOT). The routine will
return 0 on successful execution of the test, and 1 if the test
+The lists of the POST tests that should be run at power-on/normal/
+power-fail booting will be kept in the environment. Namely, the
+following environment variables will be used: post_poweron,
+powet_normal, post_slowtest.
+2.1.2. Test resu