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求救：英语修辞中的 Zeugma 和
Syllepsis 怎么区别?麻烦哪位大侠 举几个例好吗?O(∩_∩)O谢谢
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2亿+学生的选择
syllepsis与zeugma虽然貌似相同,然而却有着本质上的区别.它们的共同之处都是用一个词同时与两个或更多的词进行搭配,而且前后搭配的东西不同类,它们的区别是syllepsis所采用的搭配是自然的、合情合理的,而zeugma所采...
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扫描下载二维码Verilog HDL Syntax And Semantics Part-II
Verilog HDL Syntax And Semantics
Modules are the building blocks of Verilog designs
You create the design hierarchy by instantiating modules in other modules.
You instance a module when you use that module in another, higher-level module.
Ports allow communication between a module and its environment.
All but the top-level modules in a hierarchy have ports.
Ports can be associated by order or by name.
You declare ports to be input, output or inout. The port declaration syntax is :
[range_val:range_var] list_of_
output [range_val:range_var] list_of_
[range_val:range_var] list_of_
NOTE : As a good coding practice, there should be only one port identifier per line, as shown below
Examples : Port Declaration
// clock input
data_ // 16 bit data input bus
3 output [7:0] // 8 bit counter output
data_ // Bi-Directional data bus
You could download file port_declare.v
Examples : A complete Example in Verilog
1 module addbit (
, // first input
, // Second input
, // Carry input
, // sum output
// carry output
8 //Input declaration
12 //Ouput declaration
15 //Port Data types
21 //Code starts here
22 assign {co,sum} = a + b +
24 endmodule // End of Module addbit
You could download file addbit.v
Modules connected by port order (implicit)
Here order should match correctly. Normally it's not a good idea to connect ports implicitly. It could cause problem in debug (for example: locating the port which is causing a compile error), when any port is added or deleted.
1 //-----------------------------------------------------
2 // This is simple adder Program
3 // Design Name : adder_implicit
4 // File Name
: adder_implicit.v
5 // Function
: This program shows how implicit
port connection are done
7 // Coder
: Deepak Kumar Tala
8 //-----------------------------------------------------
9 module adder_implicit (
, // Output of the adder
, // Carry output of adder
, // first input
, // second input
// carry input
17 // Input Port Declarations
22 // Output Port Declarations
26 // Port Wires
33 // Internal variables
38 // Code Starts Here
39 addbit u0 (
43 result[0]
47 addbit u1 (
51 result[1]
55 addbit u2 (
59 result[2]
63 addbit u3 (
67 result[3]
71 endmodule // End Of Module adder
You could download file adder_implicit.v
Modules connected by name
Here the name should match with the leaf module, the order is not important.
1 //-----------------------------------------------------
2 // This is simple adder Program
3 // Design Name : adder_explicit
4 // File Name
: adder_explicit.v
5 // Function
: Here the name should match
6 // with the leaf module, the order is not important.
7 // Coder
: Deepak Kumar Tala
8 //-----------------------------------------------------
9 module adder_explicit (
, // Output of the adder
, // Carry output of adder
, // first input
, // second input
// carry input
17 // Input Port Declarations
22 // Output Port Declarations
26 // Port Wires
33 // Internal variables
38 // Code Starts Here
39 addbit u0 (
42 .ci
43 .sum
(result[0])
44 .co
47 addbit u1 (
50 .ci
51 .sum
(result[1])
52 .co
55 addbit u2 (
58 .ci
59 .sum
(result[2])
60 .co
63 addbit u3 (
66 .ci
67 .sum
(result[3])
68 .co
71 endmodule // End Of Module adder
You could download file adder_explicit.v
Instantiating a module
1 //-----------------------------------------------------
2 // This is simple parity Program
3 // Design Name : parity
4 // File Name
: parity.v
5 // Function
: This program shows how a verilog
primitive/module port connection are done
7 // Coder
8 //-----------------------------------------------------
9 module parity (
, // First input
, // Second input
, // Third Input
, // Fourth Input
17 // Input Declaration
22 // Ouput Declaration
24 // port data types
30 // Internal variables
34 // Code starts Here
35 xor u0 (out_0,a,b);
37 xor u1 (out_1,c,d);
39 xor u2 (y,out_0,out_1);
41 endmodule // End Of Module parity
You could download file parity.v
Question : What is the difference between u0 in module adder and u0 in module parity?
Port Connection Rules
Inputs : internally must always be of type net, externally the inputs can be connected to a variable of type reg or net.
Outputs : internally can be of type net or reg, externally the outputs must be connected to a variable of type net.
Inouts : internally or externally must always be type net, can only be connected to a variable net type.
Width matching : It is legal to connect internal and external ports of different sizes. But beware, synthesis tools could report problems.
Unconnected ports : unconnected ports are allowed by using a &,&.
The net data types are used to connect structure.
A net data type is required if a signal can be driven a structural connection.
Example - Implicit Unconnected Port
1 module implicit();
2 reg clk,d,rst,
5 // Here second port is not connected
6 dff u0 ( q,,clk,d,rst,pre);
8 endmodule
10 // D fli-flop
11 module dff (q, q_bar, clk, d, rst, pre);
12 input clk, d, rst,
13 output q, q_
16 assign q_bar = ~q;
18 always @ (posedge clk)
19 if (rst == 1'b1) begin
21 end else if (pre == 1'b1) begin
23 end else begin
27 endmodule
You could download file implicit.v
Example - Explicit Unconnected Port
1 module explicit();
2 reg clk,d,rst,
5 // Here q_bar is not connected
6 // We can connect ports in any order
7 dff u0 (
10 .clk
11 .q_bar
12 .rst
13 .pre
16 endmodule
18 // D fli-flop
19 module dff (q, q_bar, clk, d, rst, pre);
20 input clk, d, rst,
21 output q, q_
24 assign q_bar = ~q;
26 always @ (posedge clk)
27 if (rst == 1'b1) begin
29 end else if (pre == 1'b1) begin
31 end else begin
35 endmodule
You could download file explicit.v
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