Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstract With the dearth of dedicated radiation hardened foundries, new and novel techniques
are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IA?E) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices. Index Terms Single Event Effects, Hardened-By-Design, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercial state-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, cost-effective, and reliable manner. However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualifica what types of tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices? As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, otherquestions must be asked. How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived. Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies. The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations. III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLER With their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IA?E (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required. The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IA?E chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IA?E technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiationC hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation. The objective of this work is the technology evaluation of the CULPRiT process [3] from IA?E. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison,the cost benefit, performance, and reliability trade study can be done. In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future. IV. TEST DEVICES Three devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively. The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 ° and at a clock speeds of 3.5 MHz to 24 MHz. T hey are manufactured in Intel’s C P629.0 CHMOS III-E process. The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 ° at clock spe eds up to 25 MHz. They have a C second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes. The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two sepa the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family. V. TEST HARDWARE The 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other components of the DUT computer were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This &DUT Board& was connected to the &Main Board& by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary insome designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup. VI. TEST SOFTWARE The 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer. ? An external real-time clock for data error tag. ? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary. ? A &foul-up& routine to reset program counter if it wanders out of code space. ? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt C This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information. Logic C This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information. Memory C This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern.Compares were performed continuously and miscompares were corrected while error information and register values were transmitted. Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers C This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted. Special Function Registers (SFR) C This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted. Stack C This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with &Boot/Serial Loader& code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the &Test Controller&. The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code. The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itself or the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this report ceased, the Test Controller knew that a SEFI had occurred. This periodic data was called &telemetry&. If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII. DISCUSSION A. Single Event Latchup The main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity. B. Single Event Upset The primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some results obtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051. With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a &dc-bias& component C presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold. The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough. At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35?m library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset. IX. SUMMARY A detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results. This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application. ACKNOWLEDGEMENTS The authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).使用8051单片机验证和测试单粒子效应的加固工艺摘要随着代工业务（抗辐射加固设计的芯片制造加工厂专门从事的一项业务）的 减少，使用非专用代工业务的新技术逐步发展起来。在这篇论文中，我们将在空 间环境中讨论单粒子效应（SEE）的验证方法。课题包括需要测试的类型和设计 覆盖面（即他们是否需要验证设计库的每个应用程序？）。文章所提到的8051 单片机核心是根据美国航天局的高级微电子研究所（ IAμE）的CMOS超低功耗辐 射容错技术（CULPRiT）设计的。它是评价两个8051工业用设备单粒子效应缓和 技术的一项设计。索引词单粒子效应，加固工艺， 微控制器，辐射效应。一导言美国航天局要在空间辐射环境中最低限度地使用资源条件下， 不断努力提供最好科学方法 [ 1,2 ] 。然而，拥有最先进的技术的工业用抗辐射加固微电子 器件，几代产品中都有相对局限性，所以美国航天局的这一任务很有挑战性。本 文所介绍的方法是使用加固微创设计技术的工业代工。这通常称为加固工艺 （HBD） 。 这种使用设计程序库和自动化设计工具设计的常规加固工艺器件可为美国 宇航局提供一种解决方法，它能及时满足严格的科学性能规格，具有成本低，和 可靠性高的特点。 但是，仍然存在一个问题：常规辐射加固器件有许多和/或硅片辐射条件测 试，加固工艺的验证需要哪些类型的试验？二加固工艺检测设备的考虑美国的测试技术是要使单个器件通过如ASTM ，JEDEC的，和MIL - STD C 883 等的标准和组织的测试。通常情况下使用的是TID（Co-60）和SEE（重离子和/ 或质子）来验证器件。那么，什么是HBD器件所独有的验证呢？ 由于不采用 “常规” 工业现成 （COTS） 装置或没有固化的专用集成电路 （ASIC） ， 加固工艺的器件需要确定如何验证设计程序库而不是设备硬度。也就是说， 有 了测试芯片，我们是不是就可以在未来器件上使用相同的程序库了？ 试想，如果卖主A的设计的新的固化工艺程序库可移植性可比卖主B和C的都 好，那么A设计，测试的测试芯片就是可接受的了。9个月后，美国航天局飞行项 目就会使用卖主A的程序库设计了新器件进行组合了。这是否需要完成辐射条件 测试？回答这个问题之前，先看一下其他的问题。 如何完整地测试芯片？所有程序库元素来验证每个单元是否有足够的统计 覆盖？如果美国航天局新的设计部分使用了设计程序库或使用了没有充分描述 的部分，可能就需要全部测试了。当然，如果固化的部分工艺依靠一个进程的固 有抗辐射硬度，也可以放弃一些测试（如SEL早先的样本）。 另外， 其他考虑因素还包括运作速度和工作电压。 例如， 如果在电源电压3.3V 的条件下， 用测试芯片静态地测试单粒子效应， 所测得的数据在电源电压2.5V 操 作频率100MHz的条件下是否适用？动态因素（即非静态操作）包括单粒子瞬变 （SETs）的普及效果 。更高的频率可能更关注这些。 需要考虑的因素是，设计程序库，测试范围，铸造特点必须是已知的，并且 深刻理解测试用途。如果所有这些因素都已经具备或测试芯片已被验证，那么测 试就没有必要了。美国航天局的电子零件封装（ NEPP ）计划是为了探讨这些因 素的类型。三用8051 单片机评估加固工艺由于性能的不断提高和功耗的不断降低， 微控制器在美国航天局和国防部的 系统设计上的应用正越来越多。现在，美国航天局和国防部计划正在不断地改进 固化工艺。微控制器是一个这样的工具，正在深入量化抗辐射固化的改进。这些 计划的实例是Mission研究公司 MRC ） （ 与高级微电子研究所 （这项研究的重点） 所研制的8051 微控制器。在自然空间辐射环境中，由于这些固化工艺的使用， 美国宇航局在航天飞行中系统中使用验证技术成为必要。 8051单片机是一个行业标准架构， 被广泛接受和应用， 并作为一种开发工具。 有许多工业供应商， 他们供应这种控制器或把这种控制器集成到某种类型的系统 芯片的结构。医学研究理事会和高级微电子研究所都选择这个设备，但他们论证的是两种截然不同固化工艺。医学研究理事会的实例是使用时间锁存，需要具体 时间以确保单粒子效应减少到最低限度。高级微电子研究所采用超低功耗，以及 布局和建筑固化工艺的设计原则来实现其结果。 这些是与Aeroflex联合技术微电 子中心（ UTMC ）完全不同的方法 ，抗辐射固化的8051的工业供应商，利用抗 辐射固化进程研制自己的8051单片机。 一台设备广泛涉及的技术使得8051成为技术评价的理想载体这项工作的目 标是从高级微电子研究所得到CMOS超低功耗辐射容错进程的技术评价[ 3 ]。其 他两个过程--英特尔的8051商业设备标准和采用国家最先进的加工从达拉斯半 导体版本―是这个进程的基础，。商业研究一 一比较了他们的成本效益，性能 和可靠性。技术性能的评价是为测试微控制器开发硬件和软件。完备进程中目的 是优化测试过程以尽可能获得完整的评价。 这包括利用现有的硬件和在微控制器上运行的软件对所有子处理器进行评 价。这个进程还会使我们较完整地理解如何测试复杂的结构，如微控制器，以及 将来如何更有效地测试这些结构。四测试装置这一试验的评价使用了三款器件。首先是美国航天局的设备，这是进行评估 主要设备。其他两个设备是两种版本的商业8051 ，分别由英特尔公司和美国达 拉斯半导体制造。 英特尔的设备是无存储器型，这是经典的8052 MCS - 51单片机电路版。他 们工作环境是额定电压+5伏，温度范围在0至70 °C，时钟频率为3.5兆赫至24 兆赫。他们由英特尔P629.0 CHMOS III-E进程制造的。 达拉斯半导体器件都很相似因为他们都是ROMless 8052单片机，但他们加强 方式不同。他们的额定电压从4.25至5.5,温度在0到70 °C,时钟频率高达25兆 赫。第二次全内置串口，增设七个中断，一个看门狗定时器，一个掉电复位，双 数据指针和变速外设访问。此外，重新设计技术核心，最终使该机器周期缩短， 从而得到有效的处理能力，这大约是2.5倍（快）比标准的8052器件。不同于器 件工作所固有的功能， 这些功能没有被利用是为了达拉斯和英特尔的测试代码最 大限度地相似。 CMOS设备是MSC - 51系列的一个版本， 与超低功耗 （ULP） 进程代工许可的C8051 HDL核心兼容。C8051设备在电源电压为500毫伏运行，高压部分包括一个片上输 入/输出信号电平转换接口。 超低功耗辐射容错技术C8051设备需要两个单独的电 源电压；500毫伏和理想的接口电压。C8051是ROMless与MSC - 51系列指令系统 兼容的。五，测试硬件8051被测设备（DUT）作为实用电脑组成部分进行了测试。除了被测设备本 身，在被测设备计算机其他组成部分从立即地区辐射光束被删除。一个独特的硬 连线标识符字节所带有的小卡（每种被测设备封装类型有一个）控制被测设备， 晶体，并旁路电容器（和电压电平转换为被测设备 ） 。这种“被测设备板”是 由短60导体带状电缆连接到“主板”。各主板的所有其他组件需要被测设备计算 机完成，包括在一些设计名义上是没有必要的组件（如外部内存，外部ROM和地 址锁存器） 。 被测设备计算机和测试控制计算机是由串行电缆连接， 而两者之间的通信由控制器（即运行定制的串行接口软件）建立。这个控制器软件涉及被测设备的命 令，被测设备码的下载，和被测设备辐射前后搜集来的实时错误。1赫兹信号源 为被测设备提供了一个外部看门狗定时信号， 其看门狗输出是通过一个示波器监 测。监测电源供应来得到闭锁指示。六测试软件8051测试软件的概念很简单。它的目的是要作为一个模块化设计，为被测设 备的每一个具体部分的设计一系列小型试验程序。因为每个试验是独立的，他们 是独立加载的，在被测设备也是相互独立执行的。这将确保在测试时只有8051 被测设备所需的部分在运行，并有助于测试时发生错误的精确定位。全部测试程 序先驻存在控制器电脑中，然后通过串行接口加载到被测设备计算机。这样，个 别试验可以在任何时间被修改。还可以制定和补充额外的测试，而不会影响整体 测试设计。只有驻存在被测设备永久编码，是启动代码和在控制器PC与被测设备 建立之间的通信的串行代码装入例行程序。 所有执行的测试程序： ? 外部通用异步接收和发送装置（ UART接口），用来传送错误信息和控制器计 算机之间的通信。 ? 外部实时时钟，作为数据错误标记。 ? 看门狗，必要时为8051正常运行和重新启动的可视化确认提供测试代码。 ? “混乱”的例行程序，如果它偏离代码空间就会重置程序计数器。 ? 外部遥测数据存储器，数据传输发生中断时提供的数据备份。 应当指出的是，考虑到所有接收数据最高的可靠性，每个试验中，返回遥测 （包括时间标记）被同时送往测试控制器和遥测内存。每一个软件测试使用简要 介绍如下： 中断----这项测试用到6个可用中断矢量图中的4个来触发例程（串行，外部，定 时器0溢出，以及定时器1溢出），累加器定期地与一个已知值比较，然后启动例 行程序顺序地修改累加器的值。意外值传与寄存器信息一起传送。 逻辑----这个测试进行了一系列的逻辑和数学计算，并提供三种类型的错误鉴 定： 1 ）加法/减法， 2 ）逻辑运算，3 ） 乘法/除法。计算和期望值的所有 不匹配与其他有关寄存器信息一起传送。 存储器----这项测试间接地用0x55模式装在内部数据存储器的地址D：0x20到D： 0xff （或D ：0x20到D：0x080为CMOS超低功耗辐射容错被测设备）。当出错信 息和寄存器值被传送，不断进行比较 ，纠正。 程序计数器----取不同的偏移地址时，该程序计数器是用来取常数的。常数与已 知值进行比较，不匹配结果与有关寄存器信息一起传送。 寄存器----这项测试程序装在中的四 0,1,2,3 ） （ 段的通用寄存器或者0xAA （段 0和2 ）或0x55 （段1和3 ） 。模式交替为了测试状态字（PSW）特殊功能寄存 器，其中控制通用寄存器段的选择。然后通用寄存器段，比较他们的预期值。所 有不匹配被更正，错误信息传送。 特殊功能寄存器（ SFR）----这项测试使用可特殊功能寄存器21位中的12位的已 知静态值，然后不断地比较已知值与当前值。 不匹配与已知值和错误信息被重 新装入。 栈----这项测试通过把操作数压入和弹出堆栈进行运算。 意外值由于堆栈的错误 或堆栈指针本身和有关的寄存器信息被传送。七测试方法通过执行位于地址0x0000指令代码来启动被测设备计算机。起初，这个地址 的设备是一个以前载有“开机/串行装载机”代码的可擦写可编程只读存储器。 此代码初始化被测设备计算机及接口通过串行连接的计算机的控制， “测试控制 器”。被测设备计算机下载测试代码并把它放入程序代码存储器（位于被测设备 计算机主板） 。然后启动电路，同时进行两个功能： 被测设备的复位线保持有 效一段时间 （大约10毫秒） 并且， ； 驻存在程序码RAM的测试代码映射到地址0x0000 （在被测设备计算机内存空间该可擦写可编程只读存储器将不再被访问）。苏醒 后，从重置，通过执行地址0x0000指令代码再次启动被测设备电脑 ，但这个时 候，代码不是启动/串行装入程序代码，而是测试代码。 不论在被测设备计算机的功能性如何，测试控制计算机始终保留了强制重置/映 射功能。因此，如果测试运行没有一个单一事件功能中断（ SEFI ） 无论是被 测设备计算机本身或测试控制器可以终止了测试，并允许执行后测试功能。如果 SEFI发生，测试控制器强制重新启动到开机/串行装入程序代码然后执行后的测 试功能。 在被测设备的任何测试，被测设备行使的部分功能（例如，寄存器操作或内 部RAM的检查，或定时器操作）在最高利用可能，同时使最小定期报告的测试控 制计算机转达的被测设备计算机仍然起作用。如果此报告停止，测试控制器知道 了，一个SEFI 发生。这种定期的数据被称为“遥测” 。如果被测设备遇到了一 个错误，不能中断功能（例如，数据寄存器不匹配）通过描述的错误串口有发出 一个更多的长篇报告，并继续进行测试。八讨论A.单粒子闭锁 为什么CMOS超低功耗辐射容错设备不发生闭锁现象，主要原因是0.5伏特工 作电压低于闭锁发生需要的额定电压。此外，所使用的元件库还引进了重型双防 护方案[ 4 ] 。这个方案已被证明能多次非常有效地使CMOS 电路完全不受SEL 高达120 MeV-cm2/mg测试限制的影响 。电路工作在5,3.3和2.5伏特是可以的， 0.5伏特的CMOS超低功耗辐射容错电路也是可以的。 在一个实例中， 一个在非外延晶圆上制造的5伏的电路不受SEL的测试限制的 影响。CMOS超低功耗辐射容错设备设计即使在考虑到0.5伏特的电路时，仍选择 继续支付防护的固定成本（ ? 10-15 ％ ）。但是，考虑到实用的回偏电压， 电压可以超过现在的额定电压。 B．单粒子翻转 CMOS超低功耗辐射容错设备使用的存储单元的一级结构是单粒子防护技术 （SERT） [ 5 ] 。假设了单粒子防护技术单元拓扑和单粒子翻转节点，预计在 单粒子防护技术单元将完全不受存在内部的存储单元本身的SEUs的影响。 显然还 有其他的事情。CMOS超低功耗辐射容错8051 此处所报告的结果与CMOS超低功耗 辐射容错CCSDS无损压缩芯片（USES）获得的一些结果非常相似[ 6 ] CMOS超低 功耗辐射容错CCSDS无损压缩芯片的合成使用了与CMOS超低功耗辐射容错8051相 同的工具和程序库。 在两个有效的线性能量转移值， 37.6和58.5 MeV-cm2/mg 时，CMOS超低功 耗辐射容错CCSDS无损压缩芯片,SEU截面数据[ 7 ]作为一个频率的函数。在横截面与时钟成比例时，这两种情况下数据与线性模式拟合良好。 在线性能量转移 37.6情况下，零拦截频率基本上发生在零断面点，这表明从组合逻辑可以获得所 有这些SEUs被SETs。 线性能量转移58.5时，SET（频变）的组件是位于的“直流 偏置” 组件的上面-大概是发生内部的第二次翻转机制的单粒子防护技术元件有 效的线性能量转移闸值排在第二位。 CMOS超低功耗辐射容错设备使用的方案是基于单粒子防护技术元件容错输 入性质，此时多余的输入数据是提供给单独的存储节点。思路是多余的输入数据 是由一个总的重复组合逻辑（称为“双轨设计” ）提供， 这样一个防护上简单 的SET就不能产生翻转。因此，其他的一些翻转机制就要发生。单个粒子删除是 把一个SET放在逻辑流的两个半部分上， 逻辑流允许一个SET产生一个翻转。小 心地把双重敏感节点单粒子防护技术元件分开， 但组合逻辑路径的自动布线要与 双敏感节点足够接近。 在这一点上， CMOS超低功耗辐射容错SEU理论的解释是，在一个有效的线性 能量转移20个值中，能量集中点足够广泛，足以（和正确的位置）在组合逻辑流 的两个半部分产生一个SET。增加有效的线性能量转移使这种效应涉及的范围更 广，由此产生了更大的横截面。 此外，第二个SEU机制，开始约40-60线性能量转移，收集足够多的干扰，能 够有效地翻转的单粒子防护技术元件的冗余存储节点倍数。在这0.35微米程序 库，节点分离是几微米。 然而，因为它只需负责打破1节点操作系统在0.5伏特，具有与晶体管有效的 阈值约70毫伏，这是可能的效果得到遵守。 如图9所示的另外一个事实，即每比特内存破坏截面CMOS超低功耗辐射容错 设备和工业技术大约平等，表明元件本身已对翻转敏感。九结论利用8051微控制器作为测试工具，完成了对加固工艺（CMOS超低功耗辐射容 错技术）单粒子效应敏感性的详细比较。本文讨论了所用到的测试方法并提出了 一种比较方法，通过采集数据比较工业技术与CMOS超低功耗辐射容错技术。CMOS 超低功耗辐射容错设备有较高的线性能量转移闸值并且始终不发生闭锁现象。 除 了在线性能量转移最高值时的存储器的测试， 所有翻转粒子横截面曲线都比工业 设备的低1-2个数量级。此外，提出了解释了这些结果的理论，这个理论以CMOS 超低功耗辐射容错技术为基础。 本文还证明了把硬度量化成固化工艺的测试方法。通过在器件结构（即，不 只是一个测试芯片）应用HBD技术 ，以及等价商业设备比较结果， 人们可以有 信心在这一的硬度水平将可从该技术在任何硬件设计电路应用。致谢本文作者要感谢这项工作的发起者。 他们是美国航天局电子零部件和包封程 序（ NEPP ） ， 美国航天局的飞行计划，防卫威胁降低局（ DTRA ） 。
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