Interfacing The Serial / RS-232 Port
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Interfacing the Serial / RS232 Port
The Serial Port is harder to interface than the Parallel Port. In most cases,
any device you connect to the serial port will need the serial transmission
converted back to parallel so that it can be used. This can be done using a
UART. On the software side of things, there are many more registers that you
have to attend to than on a Standard Parallel Port. (SPP)
So what are the advantages of using serial data transfer rather than parallel?
Serial Cables can be longer than Parallel cables. The serial port transmits a '1' as -3 to -25 volts and a '0' as +3 to +25 volts where as a parallel port transmits a '0' as 0v and a '1' as 5v. Therefore the serial port can have a maximum swing of 50V compared to the parallel port which has a maximum swing of 5 Volts. Therefore cable loss is not going to be as much of a problem for serial cables than they are for parallel.
You don't need as many wires than parallel transmission. If your device needs to be mounted a far distance away from the computer then 3 core cable (Null Modem Configuration) is going to be a lot cheaper that running 19 or 25 core cable. However you must take into account the cost of the interfacing at each end.
Infra Red devices have proven quite popular recently. You may of seen many electronic diaries and palmtop computers which have infra red capabilities build in. However could you imagine transmitting 8 bits of data at the one time across the room and being able to (from the devices point of view) decipher which bits are which? Therefore serial transmission is used where one bit is sent at a time. IrDA-1 (The first infra red specifications) was capable of 115.2k baud and was interfaced into a UART. The pulse length however was cut down to 3/16th of a RS232 bit length to conserve power considering these devices are mainly used on diaries, laptops and palmtops.
Microcontroller's have also proven to be quite popular recently. Many of
these have in built SCI (Serial Communications Interfaces) which can be
used to talk to the outside world. Serial Communication reduces the pin
count of these MPU's. Only two pins are commonly used, Transmit Data (TXD)
and Receive Data (RXD) compared with at least 8 pins if you use a 8 bit
Parallel method (You may also require a Strobe).
Part 2 : Serial Ports' Registers (PC's)
Part 3 : Programming (PC's)
Part 4 : External Hardware - Interfacing Methods
Part One : Hardware (PC's)
Devices which use serial cables for their communication are split into two
categories. These are DCE (Data Communications Equipment) and DTE (Data
Terminal Equipment.) Data Communications Equipment are devices such as your
modem, TA adapter, plotter etc while Data Terminal Equipment is your
Computer or Terminal.
The electrical specifications of the serial port is contained in the EIA
(Electronics Industry Association) RS232C standard. It states many
parameters such as -
A &Space& (logic 0) will be between +3 and +25 Volts.
A &Mark& (Logic 1) will be between -3 and -25 Volts.
The region between +3 and -3 volts is undefined.
An open circuit voltage should never exceed 25 volts. (In Reference to GND)
A short circuit current should not exceed 500mA. The driver should be able to handle this without damage. (Take note of this one!)
Above is no where near a complete list of the EIA standard. Line Capacitance,
Maximum Baud Rates etc are also included. For more information please consult
the EIA RS232-C standard. It is interesting to note however, that the RS232C
standard specifies a maximum baud rate of 20,000 BPS!, which is rather slow
by today's standards. A new standard, RS-232D has been recently released.
Serial Ports come in two &sizes&, There are the D-Type 25 pin
connector and the D-Type 9 pin connector both of which are male on the back
of the PC, thus you will require a female connector on your device. Below is
a table of pin connections for the 9 pin and 25 pin D-Type connectors.
D-Type-25 Pin No.
D-Type-9 Pin No. Abbreviation Full Name
Transmit Data
Receive Data
Request To Send
Clear To Send
Data Set Ready
Signal Ground
Carrier Detect
Data Terminal Ready
Ring Indicator
Table 1 : D Type 9 Pin and D Type 25 Pin Connectors
&nbspAbbreviationFull NameFunction
&nbsp&nbsp&nbspTDTransmit DataSerial Data Output (TXD)
&nbsp&nbsp&nbspRDReceive DataSerial Data Input (RXD)
&nbsp&nbsp&nbspCTSClear to SendThis line indicates that the Modem is ready to exchange data.
&nbsp&nbsp&nbspDCDData Carrier DetectWhen the modem detects a &Carrier& from the modem at the other end of the phone line, this Line becomes active.
&nbsp&nbsp&nbspDSRData Set ReadyThis tells the UART that the modem is ready to establish a link.
&nbsp&nbsp&nbspDTRData Terminal ReadyThis is the opposite to DSR. This tells the Modem that the UART is ready to link.
&nbsp&nbsp&nbspRTSRequest To SendThis line informs the Modem that the UART is ready to exchange data.
&nbsp&nbsp&nbspRIRing IndicatorGoes active when modem detects a ringing signal from the PSTN.
A Null Modem is used to connect two DTE's together. This is commonly used as a cheap way to network games or to transfer files between computers using Zmodem Protocol, Xmodem Protocol etc. This can also be used with many Microprocessor Development Systems.
Figure 1 : Null Modem Wiring Diagram
Above is my preferred method of wiring a Null Modem. It only requires 3 wires
(TD, RD & SG) to be wired straight through thus is more cost effective to
use with long cable runs. The theory of operation is reasonably easy. The
aim is to make to computer think it is talking to a modem rather than
another computer. Any data transmitted from the first computer must be
received by the second thus TD is connected to RD. The second computer
must have the same set-up thus RD is connected to TD. Signal Ground (SG)
must also be connected so both grounds are common to each computer.
The Data Terminal Ready is looped back to Data Set Ready and Carrier Detect
on both computers. When the Data Terminal Ready is asserted active, then the
Data Set Ready and Carrier Detect immediately become active. At this point
the computer thinks the Virtual Modem to which it is connected is ready and
has detected the carrier of the other modem.
All left to worry about now is the Request to Send and Clear To Send. As
both computers communicate together at the same speed, flow control is not
needed thus these two lines are also linked together on each computer. When
the computer wishes to send data, it asserts the Request to Send high and
as it's hooked together with the Clear to Send, It immediately gets a reply
that it is ok to send and does so.
Notice that the ring indicator is not connected to anything of each end.
This line is only used to tell the computer that there is a ringing signal
on the phone line. As we don't have a modem connected to the phone line this
is left disconnected.
Figure 2 : Loopback Plug Wiring Diagram
This loopback plug can come in extremely handy when writing Serial / RS232
Communications Programs. It has the receive and transmit lines connected
together, so that anything transmitted out of the Serial Port is
immediately received by the same port. If you connect this to a Serial Port
an load a Terminal Program, anything you type will be immediately displayed
on the screen. This can be used with the examples later in this tutorial.
Please note that this is not intended for use with Diagnostic Programs and
thus will probably not work. For these programs you require a differently
wired Loop Back plug which may vary from program to program.
We have already talked briefly about DTE & DCE. A typical Data Terminal
Device is a computer and a typical Data Communications Device is a Modem.
Often people will talk about DTE to DCE or DCE to DCE speeds. DTE to DCE is
the speed between your modem and computer, sometimes referred to as your
terminal speed. This should run at faster speeds than the DCE to DCE speed.
DCE to DCE is the link between modems, sometimes called the line speed.
Most people today will have 28.8K or 33.6K modems. Therefore we should
expect the DCE to DCE speed to be either 28.8K or 33.6K. Considering the
high speed of the modem we should expect the DTE to DCE speed to be
about 115,200 BPS.(Maximum Speed of the 16550a UART) This is where some
people often fall into a trap. The communications program
which they use have settings for DCE to DTE speeds. However they see 9.6
KBPS, 14.4 KBPS etc and think it is your modem speed.
Today's Modems should have Data Compression build into them. This is very
much like PK-ZIP but the software in your modem compresses and decompresses
the data. When set up correctly you can expect compression ratios of 1:4 or
even higher. 1 to 4 compression would be typical of a text file. If we were
transferring that text file at 28.8K (DCE-DCE), then when the modem
compresses it you are actually transferring 115.2 KBPS between computers and
thus have a DCE-DTE speed of 115.2 KBPS. Thus this is why the DCE-DTE should
be much higher than your modem's connection speed.
Some modem manufacturers quote a maximum compression ratio as 1:8. Lets say
for example its on a new 33.6 KBPS modem then we may get a maximum 268,800
BPS transfer between modem and UART. If you only have a 16550a which can do
115,200 BPS tops, then you would be missing out on a extra bit of
performance. Buying a 16C650 should fix your problem with a maximum transfer
rate of 230,400 BPS.
However don't abuse your modem if you don't get these rates. These are
MAXIMUM compression ratios. In some instances if you try to send a already
compressed file, your modem can spend more time trying the compress it, thus
you get a transmission speed less than your modem's connection speed. If this
occurs try turning
off your data compression. This should be fixed on newer modems. Some files
compress easier than others thus any file which compresses easier is
naturally going to have a higher compression ratio.
So if our DTE to DCE speed is several times faster than our DCE to DCE speed
the PC can send data to your modem at 115,200 BPS. Sooner or later data is
going to get lost as buffers overflow, thus flow control is used. Flow control has two basic
varieties, Hardware or Software.
Software flow control, sometimes expressed as Xon/Xoff uses two characters
Xon and Xoff. Xon is normally indicated by the ASCII 17 character where as
the ASCII 19 character is used for Xoff. The modem will only have a small
buffer so when the computer fills it up the modem sends a Xoff character to
tell the computer to stop sending data. Once the modem has room for more
data it then sends a Xon character and the computer sends more data. This
type of flow control has the advantage that it doesn't require any more
wires as the characters are sent via the TD/RD lines. However on slow links
each character requires 10 bits which can slow communications down.
Hardware flow control is also known as RTS/CTS flow control. It uses two
wires in your serial cable rather than extra characters transmitted in your
data lines. Thus hardware flow control will not slow down transmission times
like Xon-Xoff does. When the computer wishes to send data it takes active
the Request to Send line. If the modem has room for this data, then the
modem will reply by taking active the Clear to Send line and the computer
starts sending data. If the modem does not have the room then it will not
send a Clear to Send.
UART stands for Universal Asynchronous Receiver / Transmitter. Its the little
box of tricks found on your serial card which plays the little games with
your modem or other connected devices. Most cards will have the UART's
integrated into other chips which may also control your parallel port,
games port, floppy or hard disk drives and are typically surface mount
devices. The 8250 series, which includes the 1, 16650, & 16750
UARTS are the most commonly found type in your PC. Later we will look at
other types which can be used in your homemade devices and projects.
Figure 3 : Pin Diagrams for 1 & 8250 UARTs
The 16550 is chip compatible with the 8250 & 16450. The only two differences
are pins 24 & 29. On the 8250 Pin 24 was chip select out which functioned
only as a indicator to if the chip was active or not. Pin 29 was not
connected on the
The 16550 introduced two new pins in their place. These are Transmit Ready
and Receive Ready which can be implemented with DMA (Direct Memory Access).
These Pins have two different modes of operation. Mode 0 supports single
transfer DMA where as Mode 1 supports Multi-transfer DMA.
Mode 0 is also called the 16450 mode. This mode is selected when the FIFO
buffers are disabled via Bit 0 of the FIFO Control Register or When the
FIFO buffers are enabled but DMA Mode Select = 0. (Bit 3 of FCR) In this
mode RXRDY is active low when at least one character (Byte) is present in
the Receiver Buffer. RXRDY will go inactive high when no more characters are
left in the Receiver Buffer. TXRDY will be active low when there are no
characters in the Transmit Buffer. It will go inactive high after the
first character / byte is loaded into the Transmit Buffer.
Mode 1 is when the FIFO buffers are active and the DMA Mode Select = 1. In
Mode 1, RXRDY will go active low when the trigger level is reached or when
16550 Time Out occurs and will return to inactive state when no more
characters are left in the FIFO. TXRDY will be active when no characters
are present in the Transmit Buffer and will go inactive when the FIFO
Transmit Buffer is completely Full.
All the UARTs pins are TTL compatible. That includes TD, RD, RI, DCD, DSR,
CTS, DTR and RTS which all interface into your serial plug, typically a
D-type connector. Therefore RS232 Level Converters (which we talk about in
detail later) are used. These are commonly the DS1489 Receiver and the DS1488
as the PC has +12 and -12 volt rails which can be used by these devices. The
RS232 Converters will convert the TTL signal into RS232 Logic Levels.
Pin No.NameNotes
Pin 1:8D0:D7Data Bus
Pin 9RCLKReceiver Clock Input. The frequency of this input should equal the receivers baud rate * 16
Pin 10RDReceive Data
Pin 11TDTransmit Data
Pin 12CS0Chip Select 0 - Active High
Pin 13CS1Chip Select 1 - Active High
Pin 14nCS2Chip Select 2 - Active Low
Pin 15nBAUDOUTBaud Output - Output from Programmable Baud Rate Generator. Frequency = (Baud Rate x 16)
Pin 16XINExternal Crystal Input - Used for Baud Rate Generator Oscillator
Pin 17XOUTExternal Crystal Output
Pin 18nWRWrite Line - Inverted
Pin 19WRWrite Line - Not Inverted
Pin 20VSSConnected to Common Ground
Pin 21RDRead Line - Inverted
Pin 22nRDRead Line - Not Inverted
Pin 23DDISDriver Disable. This pin goes low when CPU is reading from UART. Can be connected to Bus Transceiver in case of high capacity data bus.
Pin 24nTXRDYTransmit Ready
Pin 25nADSAddress Strobe. Used if signals are not stable during read or write cycle
Pin 26A2Address Bit 2
Pin 27A1Address Bit 1
Pin 28A0Address Bit 0
Pin 29nRXRDYReceive Ready
Pin 30INTRInterrupt Output
Pin 31nOUT2User Output 2
Pin 32nRTSRequest to Send
Pin 33nDTRData Terminal Ready
Pin 34nOUT1User Output 1
Pin 35MRMaster Reset
Pin 36nCTSClear To Send
Pin 37nDSRData Set Ready
Pin 38nDCDData Carrier Detect
Pin 39nRIRing Indicator
Pin 40VDD+ 5 Volts
Table 2 : Pin Assignments for 16550A UART
The UART requires a Clock to run. If you look at your serial card a
common crystal found is either a 1.8432 MHZ or a 18.432 MHZ Crystal.
The crystal in connected to the XIN-XOUT pins of the UART using a few
extra components which help the crystal to start oscillating. This clock
will be used for the Programmable Baud Rate Generator which directly
interfaces into the transmit timing circuits but not directly into the
receiver timing circuits. For this an external connection mast be made from
pin 15 (BaudOut) to pin 9 (Receiver clock in.) Note that the clock signal
will be at Baudrate * 16.
If you are serious about pursuing the 16550 UART used in your PC further,
then would suggest downloading a copy of the PC16550D data sheet from
sheets are available in .PDF format so you will need Adobe Acrobat Reader to
read these.
has released
the 16750 UART which has 64 Byte FIFO's. Data Sheets for the TL16C750 are
available from the Texas Instruments Site.
8250First UART in this series. It contains no scratch register. The 8250A was an improved version of the 8250 which operates faster on the bus side.
8250AThis UART is faster than the 8250 on the bus side. Looks exactly the same to software than 16450.
8250BVery similar to that of the 8250 UART.
16450Used in AT's (Improved bus speed over 8250's). Operates comfortably at 38.4KBPS. Still quite common today.
16550This was the first generation of buffered UART. It has a 16 byte buffer, however it doesn't work and is replaced with the 16550A.
16550AIs the most common UART use for high speed communications eg 14.4K & 28.8K Modems. They made sure the FIFO buffers worked on this UART.
16650Very recent breed of UART. Contains a 32 byte FIFO, Programmable X-On / X-Off characters and supports power management.
16750Produced by Texas Instruments. Contains a 64 byte FIFO.
Part Two : Serial Port's Registers (PC's)
Name AddressIRQ
Table 3 : Standard Port Addresses
Above is the standard port addresses. These should work for most P.C's. If
you just happen to be lucky enough to own a IBM P/S2 which has a
micro-channel bus, then expect a different set of addresses and IRQ's.
Just like the LPT ports, the base addresses for the COM ports can be read
from the BIOS Data Area.
Start AddressFunction
COM1's Base Address
COM2's Base Address
COM3's Base Address
COM4's Base Address
Table 4 - COM Port Addresses in the BIOS Data A
The above table shows the address at which we can find the Communications (COM)
ports addresses in the BIOS Data Area. Each address will take up 2 bytes. The
following sample program in C, shows how you can read these locations to obtain
the addresses of your communications ports.
#include &stdio.h&
#include &dos.h&
void main(void)
unsigned int far *
/* Pointer to location of Port Addresses */
/* Address of Port */
ptraddr=(unsigned int far *)0x;
for (a = 0; a &
address = *
if (address == 0)
printf("No port found for COM%d \n",a+1);
printf("Address assigned to COM%d is %Xh\n",a+1,address);
*ptraddr++;
Base AddressDLABRead/Write Abr.
Register Name
+ 0=0Write -
Transmitter Holding Buffer
Receiver Buffer
=1Read/Write -
Divisor Latch Low Byte
+ 1=0Read/Write IER
Interrupt Enable Register
=1Read/Write -
Divisor Latch High Byte
+ 2-Read IIR
Interrupt Identification Register
-Write FCR
FIFO Control Register
+ 3-Read/Write LCR
Line Control Register
+ 4-Read/Write MCR
Modem Control Register
+ 5-Read LSR
Line Status Register
+ 6-Read MSR
Modem Status Register
+ 7-Read/Write -
Scratch Register
Table 5 : Table of Registers
You will have noticed in the table of registers that there is a DLAB column.
When DLAB is set to '0' or '1' some of the registers change. This is how the
UART is able to have 12 registers (including the scratch register) through
only 8 port addresses. DLAB stands for Divisor Latch Access Bit. When DLAB
is set to '1' via the line control register, two registers become available
from which you can set your speed of communications measured in bits per
The UART will have a crystal which should oscillate around 1.8432 MHZ. The
UART incorporates a divide by 16 counter which simply divides the incoming
clock signal by 16. Assuming we had the 1.8432 MHZ clock signal, that would
leave us with a maximum, 115,200 hertz signal making the UART capable of
transmitting and receiving at 115,200 Bits Per Second (BPS). That would be
fine for some of the faster modems and devices which can handle that speed,
but others just wouldn't communicate at all. Therefore the UART is fitted
with a Programmable Baud Rate Generator which is controlled by two registers.
Lets say for example we only wanted to communicate at 2400 BPS. We worked
out that we would have to divide 115,200 by 48 to get a workable 2400 Hertz
Clock. The "Divisor", in this case 48, is stored in the two registers
controlled by the "Divisor Latch Access Bit". This divisor can be any number
which can be stored in 16 bits (ie 0 to 65535). The UART only has a 8 bit
data bus, thus this is where the two registers are used. The first register
(Base + 0) when DLAB = 1 stores the "Divisor latch low byte" where as the
second register (base + 1 when DLAB = 1) stores the "Divisor latch high
Below is a table of some more common speeds and their divisor latch high
bytes & low bytes. Note that all the divisors are shown in Hexadecimal.
Speed (BPS)
Divisor (Dec)
Divisor Latch High Byte
Divisor Latch Low Byte
Table 6 : Table of Commonly Used Baudrate Divisors
Interrupt Enable Register (IER)
Bit 7Reserved
Bit 6Reserved
Bit 5Enables Low Power Mode (16750)
Bit 4Enables Sleep Mode (16750)
Bit 3Enable Modem Status Interrupt
Bit 2Enable Receiver Line Status Interrupt
Bit 1Enable Transmitter Holding Register Empty Interrupt
Bit 0Enable Received Data Available Interrupt
Table 7 : Interrupt Enable Register
The Interrupt Enable Register could possibly be one of the easiest registers on a UART to understand. Setting Bit 0 high enables the Received Data Available Interrupt which generates an interrupt when the receiving register/FIFO contains data to be read by the CPU.
Bit 1 enables Transmit Holding Register Empty Interrupt. This interrupts the CPU when the transmitter buffer is empty.
Bit 2 enables the receiver line status interrupt. The UART will interrupt when the receiver line status changes. Likewise for bit 3 which enables the modem status interrupt.
Bits 4 to 7 are the easy ones. They are simply reserved. (If only everything was that easy!)
Bits 6 and 7Bit 6Bit 7&nbsp
01FIFO Enabled but Unusable
11FIFO Enabled
Bit 564 Byte Fifo Enabled (16750 only)
Bit 4Reserved
Bit 30Reserved on
116550 Time-out Interrupt Pending
Bits 1 and 2Bit 2Bit 1&nbsp
00Modem Status Interrupt
01Transmitter Holding Register Empty Interrupt
10Received Data Available Interrupt
11Receiver Line Status Interrupt
Bit 00Interrupt Pending
1No Interrupt Pending
Table 8 : Interrupt Identification Register
The interrupt identification register is a read only register. Bits 6 and 7
give status on the FIFO Buffer. When both bits are '0' no FIFO buffers are
active. This should be the only result you will get from a 8250 or 16450.
If bit 7 is active but bit 6 is not active then the UART has it's buffers
enabled but are unusable. This occurs on the 16550 UART where a bug in
the FIFO buffer made the FIFO's unusable. If both bits are '1' then the
FIFO buffers are enabled and fully operational.
Bits 4 and 5 are reserved. Bit 3 shows the status of the time-out interrupt on a 16550 or higher.
Lets jump to Bit 0 which shows whether an interrupt has occurred. If an interrupt has occurred it's status will shown by bits 1 and 2. These interrupts work on a priority status. The Line Status Interrupt has the highest Priority, followed by the Data Available Interrupt, then the Transmit Register Empty Interrupt and then the Modem Status Interrupt which has the lowest priority.
First In / First Out Control Register (FCR)
Bits 6 and 7Bit 7Bit 6Interrupt Trigger Level
1114 Bytes
Bit 5Enable 64 Byte FIFO (16750 only)
Bit 4Reserved
Bit 3DMA Mode Select. Change status of RXRDY & TXRDY pins from mode 1 to mode 2.
Bit 2Clear Transmit FIFO
Bit 1Clear Receive FIFO
Bit 0Enable FIFO's
Table 9 : FIFO Control Register
The FIFO register is a write only register. This register is used to control the FIFO (First In / First Out) buffers which are found on 16550's and higher.
Bit 0 enables the operation of the receive and transmit FIFO's. Writing a '0' to this bit will disable the operation of transmit and receive FIFO's, thus you will loose all data stored in these FIFO buffers.
Bit's 1 and 2 control the clearing of the transmit or receive FIFO's. Bit 1 is responsible for the receive buffer while bit 2 is responsible for the transmit buffer. Setting these bits to 1 will only clear the contents of the FIFO and will not affect the shift registers. These two bits are self resetting, thus you don't need to set the bits to '0' when finished.
Bit 3 enables the DMA mode select which is found on 16550 UARTs and higher. More on this later. Bits 4 and 5 are those easy type again, Reserved.
Bits 6 and 7 are used to set the triggering level on the Receive FIFO. For example if bit 7 was set to '1' and bit 6 was set to '0' then the trigger level is set to 8 bytes. When there is 8 bytes of data in the receive FIFO then the Received Data Available interrupt is set. See (IIR)
Line Control Register (LCR)
Bit 71Divisor Latch Access Bit
0Access to Receiver buffer, Transmitter buffer & Interrupt Enable Register
Bit 6Set Break Enable
Bits 3, 4 And 5Bit 5Bit 4Bit 3Parity Select
XX0No Parity
001Odd Parity
011Even Parity
101High Parity (Sticky)
111Low Parity (Sticky)
Bit 2Length of Stop Bit
0One Stop Bit
12 Stop bits for words of length 6,7 or 8 bits or 1.5 Stop Bits for Word lengths of 5 bits.
Bits 0 And 1Bit 1Bit 0Word Length
Table 10 : Line Control Register
The Line Control register sets the basic parameters for communication. Bit 7 is the Divisor Latch Access Bit or DLAB for short. We have already talked about what it does. (See DLAB?) Bit 6 Sets break enable. When active, the TD line goes into &Spacing& state which causes a break in the receiving UART. Setting this bit to '0' Disables the Break.
Bits 3,4 and 5 select parity. If you study the 3 bits, you will find that bit 3 controls parity. That is, if it is set to '0' then no parity is used, but if it is set to '1' then parity is used. Jumping to bit 5, we can see that it controls sticky parity. Sticky parity is simply when the parity bit is always transmitted and checked as a '1' or '0'. This has very little success in checking for errors as if the first 4 bits contain errors but the sticky parity bit contains the appropriately set bit, then a parity error will not result. Sticky high parity is the use of a '1' for the parity bit, while the opposite, sticky low parity is the use of a '0' for the parity bit.
If bit 5 controls sticky parity, then turning this bit off must produce normal parity provided bit 3 is still set to '1'. Odd parity is when the parity bit is transmitted as a '1' or '0' so that there is a odd number of 1's. Even parity must then be the parity bit produces and even number of 1's. This provides better error checking but still is not perfect, thus CRC-32 is often used for software error correction. If one bit happens to be inverted with even or odd parity set, then a parity error will occur, however if two bits are flipped in such a way that it produces the correct parity bit then an parity error will no occur.
Bit 2 sets the length of the stop bits. Setting this bit to '0' will produce one stop bit, however setting it to '1' will produce either 1.5 or 2 stop bits depending upon the word length. Note that the receiver only checks the first stop bit.
Bits 0 and 1 set the word length. This should be pretty straight forward. A word length of 8 bits is most commonly used today.
Modem Control Register (MCR)
Bit 7Reserved
Bit 6Reserved
Bit 5Autoflow Control Enabled (16750 only)
Bit 4LoopBack Mode
Bit 3Aux Output 2
Bit 2Aux Output 1
Bit 1Force Request to Send
Bit 0Force Data Terminal Ready
Table 11 : Modem Control Register
The Modem Control Register is a Read/Write Register. Bits 5,6 and 7 are reserved. Bit 4 activates the loopback mode. In Loopback mode the transmitter serial output is placed into marking state. The receiver serial input is disconnected. The transmitter out is looped back to the receiver in. DSR, CTS, RI & DCD are disconnected. DTR, RTS, OUT1 & OUT2 are connected to the modem control inputs. The modem control output pins are then place in an inactive state. In this mode any data which is placed in the transmitter registers for output is received by the receiver circuitry on the same chip and is available at the receiver buffer. This can be used to test the UARTs operation.
Aux Output 2 maybe connected to external circuitry which controls the UART-CPU interrupt process. Aux Output 1 is normally disconnected, but on some cards is used to switch between a 1.8432MHZ crystal to a 4MHZ crystal which is used for MIDI. Bits 0 and 1 simply control their relevant data lines. For example setting bit 1 to '1' makes the request to send line active.
Line Status Register (LSR)
Bit 7Error in Received FIFO
Bit 6Empty Data Holding Registers
Bit 5Empty Transmitter Holding Register
Bit 4Break Interrupt
Bit 3Framing Error
Bit 2Parity Error
Bit 1Overrun Error
Bit 0Data Ready
Table 12 : Line Status Register
The line status register is a read only register. Bit 7 is the error in received FIFO bit. This bit is high when at least one break, parity or framing error has occurred on a byte which is contained in the FIFO.
When bit 6 is set, both the transmitter holding register and the shift register are empty. The UART's holding register holds the next byte of data to be sent in parallel fashion. The shift register is used to convert the byte to serial, so that it can be transmitted over one line. When bit 5 is set, only the transmitter holding register is empty. So what's the difference between the two? When bit 6, the transmitter holding and shift registers are empty, no serial conversions are taking place so there should be no activity on the transmit data line. When bit 5 is set, the transmitter holding register is empty, thus another byte can be sent to the data port, but a serial conversion using the shift register may be taking place.
The break interrupt (Bit 4) occurs when the received data line is held in a logic state '0' (Space) for more than the time it takes to send a full word. That includes the time for the start bit, data bits, parity bits and stop bits.
A framing error (Bit 3) occurs when the last bit is not a stop bit. This may occur due to a timing error. You will most commonly encounter a framing error when using a null modem linking two computers or a protocol analyzer when the speed at which the data is being sent is different to that of what you have the UART set to receive it at.
A overrun error normally occurs when your program can't read from the port fast enough. If you don't get an incoming byte out of the register fast enough, and another byte just happens to be received, then the last byte will be lost and a overrun error will result.
Bit 0 shows data ready, which means that a byte has been received by the UART and is at the receiver buffer ready to be read.
Modem Status Register (MSR)
Bit 7Carrier Detect
Bit 6Ring Indicator
Bit 5Data Set Ready
Bit 4Clear To Send
Bit 3Delta Data Carrier Detect
Bit 2Trailing Edge Ring Indicator
Bit 1Delta Data Set Ready
Bit 0Delta Clear to Send
Table 13 : Modem Status Register
Bit 0 of the modem status register shows delta clear to send, delta meaning a change in, thus delta clear to send means that there was a change in the clear to send line, since the last read of this register. This is the same for bits 1 and 3. Bit 1 shows a change in the Data Set Ready line where as Bit 3 shows a change in the Data Carrier Detect line. Bit 2 is the Trailing Edge Ring Indicator which indicates that there was a transformation from low to high state on the Ring Indicator line.
Bits 4 to 7 show the current state of the data lines when read. Bit 7 shows Carrier Detect, Bit 6 shows Ring Indicator, Bit 5 shows Data Set Ready & Bit 4 shows the status of the Clear To Send line.
Scratch Register
The scratch register is not used for communications but rather used as a place to leave a byte of data. The only real use it has is to determine whether the UART is a B or a
and even that is not very practical today as the B was never designed for AT's and can't hack the bus speed.
Part 3 : Programming (PC's)
Part 4 : External Hardware - Interfacing Methods
25th October 2010.