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SATA IP core
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Product Description
The SATA IP Core implements the link layer and some parts of transport layer for communication between upper protocol layer managed by Host processor and PHY layer implemented by 7-series GTX. Host interface is easy interface with an embedded processor on FPGA (Microblaze and PowerPC). PHY interface is designed to support 40-bit PHY interface with 150MHz reference clock for SATA-III 6.0Gbps operation. For more detail, please visit /SATA-IP_X_E.html
Key Features and Benefits
Able to evaluate on KCU105/KC705/AC701/VC707/VC709/ZC706/ML505/ML506/SP605 board before purchasing the IPcore.
Adopted by NASA, proven high reliability
CONT primitive support for continue primitive suppression to reduce EMI .
Compact and small resource usage, suitable for multi-channel RAID system
Compliant with the Serial ATA specification revision 3.0.
Low frequency operation - IP Core and PHY clock 150MHz for SATA-III. - IP Core clock 75.0MHz and PHY clock 150MHz for SATA-II. - IP Core clock 37.5MHz and PHY clock 75MHz for SATA-I.
Simple transaction interface with Host processor or DMA Engine.
Sold more than 50 IPs all over the world
Support 40bit width PHY implemented by Kintex-7 GTX.
Support both of SATA Host and SATA Device.
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
Speed Grade
Tool Version
HW Validated?
FMAX (Mhz)
VIRTEX-7X Family
Vivado 2013.2
VIRTEX-7X Family
Vivado 2013.2
KINTEX-7 Family
Vivado 2013.2
ARTIX-7 Family
Vivado 2013.2
Zynq-7000 Family
Vivado 2013.2
KINTEX-U Family
Vivado 2014.4
IP Quality Metrics
General Information
This Data was Current On
Sep 25, 2017
Current IP Revision Number
Date Current Revision was Released
Feb 08, 2013
Release Date of First Version
Aug 26, 2008
Production Use by Xilinx Customers
Number of Successful Xilinx Customer Production Projects
Can References be Made Available?
Deliverables
IP Formats Available for Purchase
Source Code Format(s)
High-Level Model Included?
Integration Testbench Provided
Integration Test Bench Format(s)
Code Coverage Report Provided?
Functional Coverage Report Provided?
UCFs Provided?
Commercial Evaluation Board Available?
FPGA Used on Board
Kintex UltraScale
Software Drivers Provided?
Driver OS Support
Implementation
Code Optimized for Xilinx?
Standard FPGA Optimization Techniques
Other Optimization Techniques
Custom FPGA Optimization Techniques
FIFO,Core Generator
Synthesis Software Tools Supported/Version
Xilinx XST / 11.5
Static Timing Analysis Performed?
IP-XACT Metadata Included?
Verification
Is a Document Verification Plan Available?
Test Methodology
Directed Testing
Assertions
Coverage Metrics Collected
Timing Verification Performed?
Timing Verification Report Available
Simulators Supported
Xilinx lSim / 14.4
Hardware Validation
Validated on FPGA
Hardware Validation Platform Used
ML505, ML506, ML507, ML605, SP605, ML555, KC705, AC701, VC707, VC709, ZC706, KCU105
Industry Standard Compliance Testing Passed
Specific Compliance Test
Are Test Results Available?
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SATA IP core
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The SATA IP Core implements the link layer and some parts of transport layer for communication between upper protocol layer managed by Host processor and PHY layer implemented by 7-series GTX. Host interface is easy interface with an embedded processor on FPGA (Microblaze and PowerPC). PHY interface is designed to support 40-bit PHY interface with 150MHz reference clock for SATA-III 6.0Gbps operation. For more detail, please visit /SATA-IP_X_E.html
主要特性与优势
Able to evaluate on KCU105/KC705/AC701/VC707/VC709/ZC706/ML505/ML506/SP605 board before purchasing the IPcore.
Adopted by NASA, proven high reliability
CONT primitive support for continue primitive suppression to reduce EMI .
Compact and small resource usage, suitable for multi-channel RAID system
Compliant with the Serial ATA specification revision 3.0.
Low frequency operation - IP Core and PHY clock 150MHz for SATA-III. - IP Core clock 75.0MHz and PHY clock 150MHz for SATA-II. - IP Core clock 37.5MHz and PHY clock 75MHz for SATA-I.
Simple transaction interface with Host processor or DMA Engine.
Sold more than 50 IPs all over the world
Support 40bit width PHY implemented by Kintex-7 GTX.
Support both of SATA Host and SATA Device.
特色技术文档
器件实现矩阵
面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。
硬件验证？
FMAX (Mhz)
VIRTEX-7X Family
Vivado 2013.2
VIRTEX-7X Family
Vivado 2013.2
KINTEX-7 Family
Vivado 2013.2
ARTIX-7 Family
Vivado 2013.2
Zynq-7000 Family
Vivado 2013.2
KINTEX-U Family
Vivado 2014.4
IP 质量指标
数据创建日期
Sep 25, 2017
当前 IP 修订号
当前修订日期已发布
Feb 08, 2013
第一版发布日期
Aug 26, 2008
Xilinx 客户的生产使用情况
Xilinx 客户成功生产项目的数量
可否提供参考？
可供购买的 IP 格式
源代码格式
是否包含高级模型？
提供集成测试台
集成测试台格式
是否提供代码覆盖率报告？
是否提供功能覆盖率报告？
是否提供 UCF？
商业评估板是否可用？
评估板所用的 FPGA
Kintex UltraScale
是否提供软件驱动程序？
驱动程序的操作系统支持
代码是否针对 Xilinx 进行优化？
标准 FPGA 优化技术
Other Optimization Techniques
定制 FPGA 优化技术
FIFO,Core Generator
所支持的综合软件工具及版本
Xilinx XST / 11.5
是否执行静态时序分析？
是否包含 IP-XACT 元数据？
是否有可用的文档验证计划？
Directed Testing
收集的覆盖指标
是否执行时序验证？
可用的时序验证报告
所支持的仿真器
Xilinx lSim / 14.4
在 FPGA 上进行验证
所使用的硬件验证平台
ML505, ML506, ML507, ML605, SP605, ML555, KC705, AC701, VC707, VC709, ZC706, KCU105
已通过的行业标准合规测试
特定的合规测试
是否提供测试结果？
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