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stm32f2+uCos+USB通讯出现问题，寻求有经验的大神帮忙
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目前的情况的这样的，ucos移植成功，USB也移植成功。我使用了libusb编写上位机程序。当USB与PC连接好，上位机程序运行的情况下，没有任何异常，运行完美。PC能收到stm32的数据。
问题是当USB与PC连接好，但是上位机程序没运行，问题就出现了。stm32不工作了，也不说不工作，应该说是在USB发送里面死循环了。其他任务都跑不了了。
还有一个现象是USB与PC没连接，上诉问题就没出现。。。。
回复【4楼】addSeven:
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试试这个方法。
把结果反馈一下。
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回复【4楼】addSeven:
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试试这个方法。
把结果反馈一下。
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没做过，这里做过系统的人比较少。
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这问题，好像遇到过，
你是用库函数吗？用的那种USB方式？
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回复【3楼】xuande:
---------------------------------
是库函数，HID
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没做过，帮顶
还想问一下LZ，用的usb协议来做上下位机通信，通信协议会不会比串口通信复杂，还是上下位机也有相应的发送接收函数 ，像串口那样自己定个协议发送接收就好了
目前我用usb口模拟串口来和上位机通信
活着才是王道！健康是一切的前提！
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找到问题了，是堆栈爆了。
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回复【5楼】lison0103:
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确实，如果用CDC会更好用。
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回复【8楼】xuande:
---------------------------------
本来发现了一个问题，以为解决了，后来才发现还没解决。之后更换了VCP方式。也出现同样的问题。你这个方法可行，加了代码之后没出现问题。
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回复【9楼】addSeven:
---------------------------------
好消息，回头还要去感谢原作者。
对HID方式有效吗？可否验证一下？
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mark 楼主调好了吗？准备研究一下stm32接u盘
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不知道楼主有没有试过 STM32F2中，使用 FS core 从设备，HS core使用embedded phy 做host，我查了很久，class中使用鼠标、键盘等。如果有的话，可以传授下经验吗？
可以留下你的QQ号吗？ 我的QQ 是
任何一件事情，只要心甘情愿，总是能够变得简单。
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USB2SDI12/
Index: stm32f10x.h
===================================================================
--- stm32f10x.h (revision 0)
+++ stm32f10x.h (revision 3)
@@ -0,0 +1,8336 @@
******************************************************************************
stm32f10x.h
MCD Application Team
* @version V3.5.0
11-March-2011
CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
This file contains all the peripheral register's definitions, bits
definitions and memory mapping for STM32F10x Connectivity line,
High density, High density value line, Medium density,
Medium density Value line, Low density, Low density Value line
and XL-density devices.
The file is the unique include file that the application programmer
is using in the C source code, usually in main.c. This file contains:
- Configuration section that allows to select:
- The device used in the target application
- To use or not the peripheral抯 drivers in application code(i.e.
code will be based on direct access to peripheral抯 registers
rather than drivers API), this option is controlled by
&#define USE_STDPERIPH_DRIVER&
- To change few application-specific parameters such as the HSE
crystal frequency
- Data structures and the address mapping for all peripherals
- Peripheral's registers declarations and bits definition
- Macros to access peripheral抯 registers hardware
******************************************************************************
* @attention
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
* &h2&&center&& COPYRIGHT 2011 STMicroelectronics&/center&&/h2&
******************************************************************************
+/** @addtogroup CMSIS
+/** @addtogroup stm32f10x
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+#ifdef __cplusplus
+ extern &C& {
+/** @addtogroup Library_configuration_section
+/* Uncomment the line below according to the target STM32 device used in your
application
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
/* #define STM32F10X_LD */
/*!& STM32F10X_LD: STM32 Low density devices */
/* #define STM32F10X_LD_VL */
/*!& STM32F10X_LD_VL: STM32 Low density Value Line devices */
/* #define STM32F10X_MD */
/*!& STM32F10X_MD: STM32 Medium density devices */
/* #define STM32F10X_MD_VL */
/*!& STM32F10X_MD_VL: STM32 Medium density Value Line devices */
/* #define STM32F10X_HD */
/*!& STM32F10X_HD: STM32 High density devices */
/* #define STM32F10X_HD_VL */
/*!& STM32F10X_HD_VL: STM32 High density value line devices */
/* #define STM32F10X_XL */
/*!& STM32F10X_XL: STM32 XL-density devices */
/* #define STM32F10X_CL */
/*!& STM32F10X_CL: STM32 Connectivity line devices */
Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error &Please select first the target STM32F10x device used in your application (in stm32f10x.h file)&
+#if !defined
USE_STDPERIPH_DRIVER
+ * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
/*#define USE_STDPERIPH_DRIVER*/
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
used in your application
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
+#if !defined
+ #ifdef STM32F10X_CL
#define HSE_VALUE
((uint32_t)) /*!& Value of the External oscillator in Hz */
#define HSE_VALUE
((uint32_t)8000000) /*!& Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
+#define HSE_STARTUP_TIMEOUT
((uint16_t)0x0500) /*!& Time out for HSE start up */
+#define HSI_VALUE
((uint32_t)8000000) /*!& Value of the Internal oscillator in Hz*/
+ * @brief STM32F10x Standard Peripheral Library version number
+#define __STM32F10X_STDPERIPH_VERSION_MAIN
(0x03) /*!& [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1
(0x05) /*!& [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2
(0x00) /*!& [15:8]
sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC
(0x00) /*!& [7:0]
release candidate */
+#define __STM32F10X_STDPERIPH_VERSION
( (__STM32F10X_STDPERIPH_VERSION_MAIN && 24)\
|(__STM32F10X_STDPERIPH_VERSION_SUB1 && 16)\
|(__STM32F10X_STDPERIPH_VERSION_SUB2 && 8)\
|(__STM32F10X_STDPERIPH_VERSION_RC))
+/** @addtogroup Configuration_section_for_CMSIS
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT
1 /*!& STM32 XL-density devices provide an MPU */
+ #define __MPU_PRESENT
0 /*!& Other STM32 devices does not provide an MPU */
+#endif /* STM32F10X_XL */
+#define __NVIC_PRIO_BITS
4 /*!& STM32 uses 4 Bits for the Priority Levels
+#define __Vendor_SysTickConfig
0 /*!& Set to 1 if different SysTick Config is used */
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
in @ref Library_configuration_section
+typedef enum IRQn
Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn
/*!& 2 Non Maskable Interrupt
MemoryManagement_IRQn
/*!& 4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn
/*!& 5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn
/*!& 6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn
/*!& 11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn
/*!& 12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn
/*!& 14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn
/*!& 15 Cortex-M3 System Tick Interrupt
STM32 specific Interrupt Numbers *********************************************************/
/*!& Window WatchDog Interrupt
/*!& PVD through EXTI Line detection Interrupt
TAMPER_IRQn
/*!& Tamper Interrupt
/*!& RTC global Interrupt
FLASH_IRQn
/*!& FLASH global Interrupt
/*!& RCC global Interrupt
EXTI0_IRQn
/*!& EXTI Line0 Interrupt
EXTI1_IRQn
/*!& EXTI Line1 Interrupt
EXTI2_IRQn
/*!& EXTI Line2 Interrupt
EXTI3_IRQn
/*!& EXTI Line3 Interrupt
EXTI4_IRQn
/*!& EXTI Line4 Interrupt
DMA1_Channel1_IRQn
/*!& DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn
/*!& DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn
/*!& DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn
/*!& DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn
/*!& DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn
/*!& DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn
/*!& DMA1 Channel 7 global Interrupt
+#ifdef STM32F10X_LD
ADC1_2_IRQn
/*!& ADC1 and ADC2 global Interrupt
USB_HP_CAN1_TX_IRQn
/*!& USB Device High Priority or CAN1 TX Interrupts
USB_LP_CAN1_RX0_IRQn
/*!& USB Device Low Priority or CAN1 RX0 Interrupts
CAN1_RX1_IRQn
/*!& CAN1 RX1 Interrupt
CAN1_SCE_IRQn
/*!& CAN1 SCE Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_IRQn
/*!& TIM1 Break Interrupt
TIM1_UP_IRQn
/*!& TIM1 Update Interrupt
TIM1_TRG_COM_IRQn
/*!& TIM1 Trigger and Commutation Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
/*!& SPI1 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
USBWakeUp_IRQn
/*!& USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_LD */
+#ifdef STM32F10X_LD_VL
/*!& ADC1 global Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_TIM15_IRQn
/*!& TIM1 Break and TIM15 Interrupts
TIM1_UP_TIM16_IRQn
/*!& TIM1 Update and TIM16 Interrupts
TIM1_TRG_COM_TIM17_IRQn
/*!& TIM1 Trigger and Commutation and TIM17 Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
/*!& SPI1 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
/*!& HDMI-CEC Interrupt
TIM6_DAC_IRQn
/*!& TIM6 and DAC underrun Interrupt
/*!& TIM7 Interrupt
+#endif /* STM32F10X_LD_VL */
+#ifdef STM32F10X_MD
ADC1_2_IRQn
/*!& ADC1 and ADC2 global Interrupt
USB_HP_CAN1_TX_IRQn
/*!& USB Device High Priority or CAN1 TX Interrupts
USB_LP_CAN1_RX0_IRQn
/*!& USB Device Low Priority or CAN1 RX0 Interrupts
CAN1_RX1_IRQn
/*!& CAN1 RX1 Interrupt
CAN1_SCE_IRQn
/*!& CAN1 SCE Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_IRQn
/*!& TIM1 Break Interrupt
TIM1_UP_IRQn
/*!& TIM1 Update Interrupt
TIM1_TRG_COM_IRQn
/*!& TIM1 Trigger and Commutation Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
USBWakeUp_IRQn
/*!& USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_MD */
+#ifdef STM32F10X_MD_VL
/*!& ADC1 global Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_TIM15_IRQn
/*!& TIM1 Break and TIM15 Interrupts
TIM1_UP_TIM16_IRQn
/*!& TIM1 Update and TIM16 Interrupts
TIM1_TRG_COM_TIM17_IRQn
/*!& TIM1 Trigger and Commutation and TIM17 Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
/*!& HDMI-CEC Interrupt
TIM6_DAC_IRQn
/*!& TIM6 and DAC underrun Interrupt
/*!& TIM7 Interrupt
+#endif /* STM32F10X_MD_VL */
+#ifdef STM32F10X_HD
ADC1_2_IRQn
/*!& ADC1 and ADC2 global Interrupt
USB_HP_CAN1_TX_IRQn
/*!& USB Device High Priority or CAN1 TX Interrupts
USB_LP_CAN1_RX0_IRQn
/*!& USB Device Low Priority or CAN1 RX0 Interrupts
CAN1_RX1_IRQn
/*!& CAN1 RX1 Interrupt
CAN1_SCE_IRQn
/*!& CAN1 SCE Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_IRQn
/*!& TIM1 Break Interrupt
TIM1_UP_IRQn
/*!& TIM1 Update Interrupt
TIM1_TRG_COM_IRQn
/*!& TIM1 Trigger and Commutation Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
USBWakeUp_IRQn
/*!& USB Device WakeUp from suspend through EXTI Line Interrupt */
TIM8_BRK_IRQn
/*!& TIM8 Break Interrupt
TIM8_UP_IRQn
/*!& TIM8 Update Interrupt
TIM8_TRG_COM_IRQn
/*!& TIM8 Trigger and Commutation Interrupt
TIM8_CC_IRQn
/*!& TIM8 Capture Compare Interrupt
/*!& ADC3 global Interrupt
/*!& FSMC global Interrupt
/*!& SDIO global Interrupt
/*!& TIM5 global Interrupt
/*!& SPI3 global Interrupt
UART4_IRQn
/*!& UART4 global Interrupt
UART5_IRQn
/*!& UART5 global Interrupt
/*!& TIM6 global Interrupt
/*!& TIM7 global Interrupt
DMA2_Channel1_IRQn
/*!& DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn
/*!& DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn
/*!& DMA2 Channel 3 global Interrupt
DMA2_Channel4_5_IRQn
/*!& DMA2 Channel 4 and Channel 5 global Interrupt
+#endif /* STM32F10X_HD */
+#ifdef STM32F10X_HD_VL
/*!& ADC1 global Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_TIM15_IRQn
/*!& TIM1 Break and TIM15 Interrupts
TIM1_UP_TIM16_IRQn
/*!& TIM1 Update and TIM16 Interrupts
TIM1_TRG_COM_TIM17_IRQn
/*!& TIM1 Trigger and Commutation and TIM17 Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
/*!& HDMI-CEC Interrupt
TIM12_IRQn
/*!& TIM12 global Interrupt
TIM13_IRQn
/*!& TIM13 global Interrupt
TIM14_IRQn
/*!& TIM14 global Interrupt
/*!& TIM5 global Interrupt
/*!& SPI3 global Interrupt
UART4_IRQn
/*!& UART4 global Interrupt
UART5_IRQn
/*!& UART5 global Interrupt
TIM6_DAC_IRQn
/*!& TIM6 and DAC underrun Interrupt
/*!& TIM7 Interrupt
DMA2_Channel1_IRQn
/*!& DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn
/*!& DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn
/*!& DMA2 Channel 3 global Interrupt
DMA2_Channel4_5_IRQn
/*!& DMA2 Channel 4 and Channel 5 global Interrupt
DMA2_Channel5_IRQn
/*!& DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
mapped at position 60 only if the MISC_REMAP bit in
the AFIO_MAPR2 register is set)
+#endif /* STM32F10X_HD_VL */
+#ifdef STM32F10X_XL
ADC1_2_IRQn
/*!& ADC1 and ADC2 global Interrupt
USB_HP_CAN1_TX_IRQn
/*!& USB Device High Priority or CAN1 TX Interrupts
USB_LP_CAN1_RX0_IRQn
/*!& USB Device Low Priority or CAN1 RX0 Interrupts
CAN1_RX1_IRQn
/*!& CAN1 RX1 Interrupt
CAN1_SCE_IRQn
/*!& CAN1 SCE Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_TIM9_IRQn
/*!& TIM1 Break Interrupt and TIM9 global Interrupt
TIM1_UP_TIM10_IRQn
/*!& TIM1 Update Interrupt and TIM10 global Interrupt
TIM1_TRG_COM_TIM11_IRQn
/*!& TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
USBWakeUp_IRQn
/*!& USB Device WakeUp from suspend through EXTI Line Interrupt */
TIM8_BRK_TIM12_IRQn
/*!& TIM8 Break Interrupt and TIM12 global Interrupt
TIM8_UP_TIM13_IRQn
/*!& TIM8 Update Interrupt and TIM13 global Interrupt
TIM8_TRG_COM_TIM14_IRQn
/*!& TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
TIM8_CC_IRQn
/*!& TIM8 Capture Compare Interrupt
/*!& ADC3 global Interrupt
/*!& FSMC global Interrupt
/*!& SDIO global Interrupt
/*!& TIM5 global Interrupt
/*!& SPI3 global Interrupt
UART4_IRQn
/*!& UART4 global Interrupt
UART5_IRQn
/*!& UART5 global Interrupt
/*!& TIM6 global Interrupt
/*!& TIM7 global Interrupt
DMA2_Channel1_IRQn
/*!& DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn
/*!& DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn
/*!& DMA2 Channel 3 global Interrupt
DMA2_Channel4_5_IRQn
/*!& DMA2 Channel 4 and Channel 5 global Interrupt
+#endif /* STM32F10X_XL */
+#ifdef STM32F10X_CL
ADC1_2_IRQn
/*!& ADC1 and ADC2 global Interrupt
CAN1_TX_IRQn
/*!& USB Device High Priority or CAN1 TX Interrupts
CAN1_RX0_IRQn
/*!& USB Device Low Priority or CAN1 RX0 Interrupts
CAN1_RX1_IRQn
/*!& CAN1 RX1 Interrupt
CAN1_SCE_IRQn
/*!& CAN1 SCE Interrupt
EXTI9_5_IRQn
/*!& External Line[9:5] Interrupts
TIM1_BRK_IRQn
/*!& TIM1 Break Interrupt
TIM1_UP_IRQn
/*!& TIM1 Update Interrupt
TIM1_TRG_COM_IRQn
/*!& TIM1 Trigger and Commutation Interrupt
TIM1_CC_IRQn
/*!& TIM1 Capture Compare Interrupt
/*!& TIM2 global Interrupt
/*!& TIM3 global Interrupt
/*!& TIM4 global Interrupt
I2C1_EV_IRQn
/*!& I2C1 Event Interrupt
I2C1_ER_IRQn
/*!& I2C1 Error Interrupt
I2C2_EV_IRQn
/*!& I2C2 Event Interrupt
I2C2_ER_IRQn
/*!& I2C2 Error Interrupt
/*!& SPI1 global Interrupt
/*!& SPI2 global Interrupt
USART1_IRQn
/*!& USART1 global Interrupt
USART2_IRQn
/*!& USART2 global Interrupt
USART3_IRQn
/*!& USART3 global Interrupt
EXTI15_10_IRQn
/*!& External Line[15:10] Interrupts
RTCAlarm_IRQn
/*!& RTC Alarm through EXTI Line Interrupt
OTG_FS_WKUP_IRQn
/*!& USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
/*!& TIM5 global Interrupt
/*!& SPI3 global Interrupt
UART4_IRQn
/*!& UART4 global Interrupt
UART5_IRQn
/*!& UART5 global Interrupt
/*!& TIM6 global Interrupt
/*!& TIM7 global Interrupt
DMA2_Channel1_IRQn
/*!& DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn
/*!& DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn
/*!& DMA2 Channel 3 global Interrupt
DMA2_Channel4_IRQn
/*!& DMA2 Channel 4 global Interrupt
DMA2_Channel5_IRQn
/*!& DMA2 Channel 5 global Interrupt
/*!& Ethernet global Interrupt
ETH_WKUP_IRQn
/*!& Ethernet Wakeup through EXTI line Interrupt
CAN2_TX_IRQn
/*!& CAN2 TX Interrupt
CAN2_RX0_IRQn
/*!& CAN2 RX0 Interrupt
CAN2_RX1_IRQn
/*!& CAN2 RX1 Interrupt
CAN2_SCE_IRQn
/*!& CAN2 SCE Interrupt
OTG_FS_IRQn
/*!& USB OTG FS global Interrupt
+#endif /* STM32F10X_CL */
+#include &core_cm3.h&
+#include &system_stm32f10x.h&
+#include &stdint.h&
+/** @addtogroup Exported_types
+/*!& STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t
+typedef int16_t s16;
+typedef int8_t
+typedef const int32_t sc32;
/*!& Read Only */
+typedef const int16_t sc16;
/*!& Read Only */
+typedef const int8_t sc8;
/*!& Read Only */
+typedef __IO int32_t
+typedef __IO int16_t
+typedef __IO int8_t
+typedef __I int32_t vsc32;
/*!& Read Only */
+typedef __I int16_t vsc16;
/*!& Read Only */
+typedef __I int8_t vsc8;
/*!& Read Only */
+typedef uint32_t
+typedef uint16_t u16;
+typedef uint8_t
+typedef const uint32_t uc32;
/*!& Read Only */
+typedef const uint16_t uc16;
/*!& Read Only */
+typedef const uint8_t uc8;
/*!& Read Only */
+typedef __IO uint32_t
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t
+typedef __I uint32_t vuc32;
/*!& Read Only */
+typedef __I uint16_t vuc16;
/*!& Read Only */
+typedef __I uint8_t vuc8;
/*!& Read Only */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITS
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalS
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorS
+/*!& STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut
HSE_STARTUP_TIMEOUT
+#define HSE_Value
+#define HSI_Value
+/** @addtogroup Peripheral_registers_structures
* @brief Analog to Digital Converter
+typedef struct
__IO uint32_t SR;
__IO uint32_t CR1;
__IO uint32_t CR2;
__IO uint32_t SMPR1;
__IO uint32_t SMPR2;
__IO uint32_t JOFR1;
__IO uint32_t JOFR2;
__IO uint32_t JOFR3;
__IO uint32_t JOFR4;
__IO uint32_t HTR;
__IO uint32_t LTR;
__IO uint32_t SQR1;
__IO uint32_t SQR2;
__IO uint32_t SQR3;
__IO uint32_t JSQR;
__IO uint32_t JDR1;
__IO uint32_t JDR2;
__IO uint32_t JDR3;
__IO uint32_t JDR4;
__IO uint32_t DR;
+} ADC_TypeD
* @brief Backup Registers
+typedef struct
RESERVED0;
__IO uint16_t DR1;
RESERVED1;
__IO uint16_t DR2;
RESERVED2;
__IO uint16_t DR3;
RESERVED3;
__IO uint16_t DR4;
RESERVED4;
__IO uint16_t DR5;
RESERVED5;
__IO uint16_t DR6;
RESERVED6;
__IO uint16_t DR7;
RESERVED7;
__IO uint16_t DR8;
RESERVED8;
__IO uint16_t DR9;
RESERVED9;
__IO uint16_t DR10;
RESERVED10;
__IO uint16_t RTCCR;
RESERVED11;
__IO uint16_t CR;
RESERVED12;
__IO uint16_t CSR;
RESERVED13[5];
__IO uint16_t DR11;
RESERVED14;
__IO uint16_t DR12;
RESERVED15;
__IO uint16_t DR13;
RESERVED16;
__IO uint16_t DR14;
RESERVED17;
__IO uint16_t DR15;
RESERVED18;
__IO uint16_t DR16;
RESERVED19;
__IO uint16_t DR17;
RESERVED20;
__IO uint16_t DR18;
RESERVED21;
__IO uint16_t DR19;
RESERVED22;
__IO uint16_t DR20;
RESERVED23;
__IO uint16_t DR21;
RESERVED24;
__IO uint16_t DR22;
RESERVED25;
__IO uint16_t DR23;
RESERVED26;
__IO uint16_t DR24;
RESERVED27;
__IO uint16_t DR25;
RESERVED28;
__IO uint16_t DR26;
RESERVED29;
__IO uint16_t DR27;
RESERVED30;
__IO uint16_t DR28;
RESERVED31;
__IO uint16_t DR29;
RESERVED32;
__IO uint16_t DR30;
RESERVED33;
__IO uint16_t DR31;
RESERVED34;
__IO uint16_t DR32;
RESERVED35;
__IO uint16_t DR33;
RESERVED36;
__IO uint16_t DR34;
RESERVED37;
__IO uint16_t DR35;
RESERVED38;
__IO uint16_t DR36;
RESERVED39;
__IO uint16_t DR37;
RESERVED40;
__IO uint16_t DR38;
RESERVED41;
__IO uint16_t DR39;
RESERVED42;
__IO uint16_t DR40;
RESERVED43;
__IO uint16_t DR41;
RESERVED44;
__IO uint16_t DR42;
RESERVED45;
+} BKP_TypeD
* @brief Controller Area Network TxMailBox
+typedef struct
__IO uint32_t TIR;
__IO uint32_t TDTR;
__IO uint32_t TDLR;
__IO uint32_t TDHR;
+} CAN_TxMailBox_TypeD
* @brief Controller Area Network FIFOMailBox
+typedef struct
__IO uint32_t RIR;
__IO uint32_t RDTR;
__IO uint32_t RDLR;
__IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeD
* @brief Controller Area Network FilterRegister
+typedef struct
__IO uint32_t FR1;
__IO uint32_t FR2;
+} CAN_FilterRegister_TypeD
* @brief Controller Area Network
+typedef struct
__IO uint32_t MCR;
__IO uint32_t MSR;
__IO uint32_t TSR;
__IO uint32_t RF0R;
__IO uint32_t RF1R;
__IO uint32_t IER;
__IO uint32_t ESR;
__IO uint32_t BTR;
RESERVED0[88];
CAN_TxMailBox_TypeDef sTxMailBox[3];
CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
RESERVED1[12];
__IO uint32_t FMR;
__IO uint32_t FM1R;
RESERVED2;
__IO uint32_t FS1R;
RESERVED3;
__IO uint32_t FFA1R;
RESERVED4;
__IO uint32_t FA1R;
RESERVED5[8];
+#ifndef STM32F10X_CL
CAN_FilterRegister_TypeDef sFilterRegister[14];
CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */
+} CAN_TypeD
* @brief Consumer Electronics Control (CEC)
+typedef struct
__IO uint32_t CFGR;
__IO uint32_t OAR;
__IO uint32_t PRES;
__IO uint32_t ESR;
__IO uint32_t CSR;
__IO uint32_t TXD;
__IO uint32_t RXD;
+} CEC_TypeD
* @brief CRC calculation unit
+typedef struct
__IO uint32_t DR;
__IO uint8_t
RESERVED0;
RESERVED1;
__IO uint32_t CR;
+} CRC_TypeD
* @brief Digital to Analog Converter
+typedef struct
__IO uint32_t CR;
__IO uint32_t SWTRIGR;
__IO uint32_t DHR12R1;
__IO uint32_t DHR12L1;
__IO uint32_t DHR8R1;
__IO uint32_t DHR12R2;
__IO uint32_t DHR12L2;
__IO uint32_t DHR8R2;
__IO uint32_t DHR12RD;
__IO uint32_t DHR12LD;
__IO uint32_t DHR8RD;
__IO uint32_t DOR1;
__IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
__IO uint32_t SR;
+} DAC_TypeD
* @brief Debug MCU
+typedef struct
__IO uint32_t IDCODE;
__IO uint32_t CR;
+}DBGMCU_TypeD
* @brief DMA Controller
+typedef struct
__IO uint32_t CCR;
__IO uint32_t CNDTR;
__IO uint32_t CPAR;
__IO uint32_t CMAR;
+} DMA_Channel_TypeD
+typedef struct
__IO uint32_t ISR;
__IO uint32_t IFCR;
+} DMA_TypeD
* @brief Ethernet MAC
+typedef struct
__IO uint32_t MACCR;
__IO uint32_t MACFFR;
__IO uint32_t MACHTHR;
__IO uint32_t MACHTLR;
__IO uint32_t MACMIIAR;
__IO uint32_t MACMIIDR;
__IO uint32_t MACFCR;
__IO uint32_t MACVLANTR;
uint32_t RESERVED0[2];
__IO uint32_t MACRWUFFR;
__IO uint32_t MACPMTCSR;
uint32_t RESERVED1[2];
__IO uint32_t MACSR;
__IO uint32_t MACIMR;
__IO uint32_t MACA0HR;
__IO uint32_t MACA0LR;
__IO uint32_t MACA1HR;
__IO uint32_t MACA1LR;
__IO uint32_t MACA2HR;
__IO uint32_t MACA2LR;
__IO uint32_t MACA3HR;
__IO uint32_t MACA3LR;
uint32_t RESERVED2[40];
__IO uint32_t MMCCR;
__IO uint32_t MMCRIR;
__IO uint32_t MMCTIR;
__IO uint32_t MMCRIMR;
__IO uint32_t MMCTIMR;
uint32_t RESERVED3[14];
__IO uint32_t MMCTGFSCCR;
__IO uint32_t MMCTGFMSCCR;
uint32_t RESERVED4[5];
__IO uint32_t MMCTGFCR;
uint32_t RESERVED5[10];
__IO uint32_t MMCRFCECR;
__IO uint32_t MMCRFAECR;
uint32_t RESERVED6[10];
__IO uint32_t MMCRGUFCR;
uint32_t RESERVED7[334];
__IO uint32_t PTPTSCR;
__IO uint32_t PTPSSIR;
__IO uint32_t PTPTSHR;
__IO uint32_t PTPTSLR;
__IO uint32_t PTPTSHUR;
__IO uint32_t PTPTSLUR;
__IO uint32_t PTPTSAR;
__IO uint32_t PTPTTHR;
__IO uint32_t PTPTTLR;
uint32_t RESERVED8[567];
__IO uint32_t DMABMR;
__IO uint32_t DMATPDR;
__IO uint32_t DMARPDR;
__IO uint32_t DMARDLAR;
__IO uint32_t DMATDLAR;
__IO uint32_t DMASR;
__IO uint32_t DMAOMR;
__IO uint32_t DMAIER;
__IO uint32_t DMAMFBOCR;
uint32_t RESERVED9[9];
__IO uint32_t DMACHTDR;
__IO uint32_t DMACHRDR;
__IO uint32_t DMACHTBAR;
__IO uint32_t DMACHRBAR;
+} ETH_TypeD
* @brief External Interrupt/Event Controller
+typedef struct
__IO uint32_t IMR;
__IO uint32_t EMR;
__IO uint32_t RTSR;
__IO uint32_t FTSR;
__IO uint32_t SWIER;
__IO uint32_t PR;
+} EXTI_TypeD
* @brief FLASH Registers
+typedef struct
__IO uint32_t ACR;
__IO uint32_t KEYR;
__IO uint32_t OPTKEYR;
__IO uint32_t SR;
__IO uint32_t CR;
__IO uint32_t AR;
__IO uint32_t RESERVED;
__IO uint32_t OBR;
__IO uint32_t WRPR;
+#ifdef STM32F10X_XL
uint32_t RESERVED1[8];
__IO uint32_t KEYR2;
uint32_t RESERVED2;
__IO uint32_t SR2;
__IO uint32_t CR2;
__IO uint32_t AR2;
+#endif /* STM32F10X_XL */
+} FLASH_TypeD
* @brief Option Bytes Registers
+typedef struct
__IO uint16_t RDP;
__IO uint16_t USER;
__IO uint16_t Data0;
__IO uint16_t Data1;
__IO uint16_t WRP0;
__IO uint16_t WRP1;
__IO uint16_t WRP2;
__IO uint16_t WRP3;
+} OB_TypeD
* @brief Flexible Static Memory Controller
+typedef struct
__IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeD
* @brief Flexible Static Memory Controller Bank1E
+typedef struct
__IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeD
* @brief Flexible Static Memory Controller Bank2
+typedef struct
__IO uint32_t PCR2;
__IO uint32_t SR2;
__IO uint32_t PMEM2;
__IO uint32_t PATT2;
RESERVED0;
__IO uint32_t ECCR2;
+} FSMC_Bank2_TypeD
* @brief Flexible Static Memory Controller Bank3
+typedef struct
__IO uint32_t PCR3;
__IO uint32_t SR3;
__IO uint32_t PMEM3;
__IO uint32_t PATT3;
RESERVED0;
__IO uint32_t ECCR3;
+} FSMC_Bank3_TypeD
* @brief Flexible Static Memory Controller Bank4
+typedef struct
__IO uint32_t PCR4;
__IO uint32_t SR4;
__IO uint32_t PMEM4;
__IO uint32_t PATT4;
__IO uint32_t PIO4;
+} FSMC_Bank4_TypeD
* @brief General Purpose I/O
+typedef struct
__IO uint32_t CRL;
__IO uint32_t CRH;
__IO uint32_t IDR;
__IO uint32_t ODR;
__IO uint32_t BSRR;
__IO uint32_t BRR;
__IO uint32_t LCKR;
+} GPIO_TypeD
* @brief Alternate Function I/O
+typedef struct
__IO uint32_t EVCR;
__IO uint32_t MAPR;
__IO uint32_t EXTICR[4];
uint32_t RESERVED0;
__IO uint32_t MAPR2;
+} AFIO_TypeD
* @brief Inter Integrated Circuit Interface
+typedef struct
__IO uint16_t CR1;
RESERVED0;
__IO uint16_t CR2;
RESERVED1;
__IO uint16_t OAR1;
RESERVED2;
__IO uint16_t OAR2;
RESERVED3;
__IO uint16_t DR;
RESERVED4;
__IO uint16_t SR1;
RESERVED5;
__IO uint16_t SR2;
RESERVED6;
__IO uint16_t CCR;
RESERVED7;
__IO uint16_t TRISE;
RESERVED8;
+} I2C_TypeD
* @brief Independent WATCHDOG
+typedef struct
__IO uint32_t KR;
__IO uint32_t PR;
__IO uint32_t RLR;
__IO uint32_t SR;
+} IWDG_TypeD
* @brief Power Control
+typedef struct
__IO uint32_t CR;
__IO uint32_t CSR;
+} PWR_TypeD
* @brief Reset and Clock Control
+typedef struct
__IO uint32_t CR;
__IO uint32_t CFGR;
__IO uint32_t CIR;
__IO uint32_t APB2RSTR;
__IO uint32_t APB1RSTR;
__IO uint32_t AHBENR;
__IO uint32_t APB2ENR;
__IO uint32_t APB1ENR;
__IO uint32_t BDCR;
__IO uint32_t CSR;
+#ifdef STM32F10X_CL
__IO uint32_t AHBRSTR;
__IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
uint32_t RESERVED0;
__IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
+} RCC_TypeD
* @brief Real-Time Clock
+typedef struct
__IO uint16_t CRH;
RESERVED0;
__IO uint16_t CRL;
RESERVED1;
__IO uint16_t PRLH;
RESERVED2;
__IO uint16_t PRLL;
RESERVED3;
__IO uint16_t DIVH;
RESERVED4;
__IO uint16_t DIVL;
RESERVED5;
__IO uint16_t CNTH;
RESERVED6;
__IO uint16_t CNTL;
RESERVED7;
__IO uint16_t ALRH;
RESERVED8;
__IO uint16_t ALRL;
RESERVED9;
+} RTC_TypeD
* @brief SD host Interface
+typedef struct
__IO uint32_t POWER;
__IO uint32_t CLKCR;
__IO uint32_t ARG;
__IO uint32_t CMD;
__I uint32_t RESPCMD;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__I uint32_t RESP4;
__IO uint32_t DTIMER;
__IO uint32_t DLEN;
__IO uint32_t DCTRL;
__I uint32_t DCOUNT;
__I uint32_t STA;
__IO uint32_t ICR;
__IO uint32_t MASK;
RESERVED0[2];
__I uint32_t FIFOCNT;
RESERVED1[13];
__IO uint32_t FIFO;
+} SDIO_TypeD
* @brief Serial Peripheral Interface
+typedef struct
__IO uint16_t CR1;
RESERVED0;
__IO uint16_t CR2;
RESERVED1;
__IO uint16_t SR;
RESERVED2;
__IO uint16_t DR;
RESERVED3;
__IO uint16_t CRCPR;
RESERVED4;
__IO uint16_t RXCRCR;
RESERVED5;
__IO uint16_t TXCRCR;
RESERVED6;
__IO uint16_t I2SCFGR;
RESERVED7;
__IO uint16_t I2SPR;
RESERVED8;
+} SPI_TypeD
* @brief TIM
+typedef struct
__IO uint16_t CR1;
RESERVED0;
__IO uint16_t CR2;
RESERVED1;
__IO uint16_t SMCR;
RESERVED2;
__IO uint16_t DIER;
RESERVED3;
__IO uint16_t SR;
RESERVED4;
__IO uint16_t EGR;
RESERVED5;
__IO uint16_t CCMR1;
RESERVED6;
__IO uint16_t CCMR2;
RESERVED7;
__IO uint16_t CCER;
RESERVED8;
__IO uint16_t CNT;
RESERVED9;
__IO uint16_t PSC;
RESERVED10;
__IO uint16_t ARR;
RESERVED11;
__IO uint16_t RCR;
RESERVED12;
__IO uint16_t CCR1;
RESERVED13;
__IO uint16_t CCR2;
RESERVED14;
__IO uint16_t CCR3;
RESERVED15;
__IO uint16_t CCR4;
RESERVED16;
__IO uint16_t BDTR;
RESERVED17;
__IO uint16_t DCR;
RESERVED18;
__IO uint16_t DMAR;
RESERVED19;
+} TIM_TypeD
* @brief Universal Synchronous Asynchronous Receiver Transmitter
+typedef struct
__IO uint16_t SR;
RESERVED0;
__IO uint16_t DR;
RESERVED1;
__IO uint16_t BRR;
RESERVED2;
__IO uint16_t CR1;
RESERVED3;
__IO uint16_t CR2;
RESERVED4;
__IO uint16_t CR3;
RESERVED5;
__IO uint16_t GTPR;
RESERVED6;
+} USART_TypeD
* @brief Window WATCHDOG
+typedef struct
__IO uint32_t CR;
__IO uint32_t CFR;
__IO uint32_t SR;
+} WWDG_TypeD
+/** @addtogroup Peripheral_memory_map
+#define FLASH_BASE
((uint32_t)0x) /*!& FLASH base address in the alias region */
+#define SRAM_BASE
((uint32_t)0x) /*!& SRAM base address in the alias region */
+#define PERIPH_BASE
((uint32_t)0x) /*!& Peripheral base address in the alias region */
+#define SRAM_BB_BASE
((uint32_t)0x) /*!& SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE
((uint32_t)0x) /*!& Peripheral base address in the bit-band region */
+#define FSMC_R_BASE
((uint32_t)0xA0000000) /*!& FSMC registers base address */
+/*!& Peripheral memory map */
+#define APB1PERIPH_BASE
PERIPH_BASE
+#define APB2PERIPH_BASE
(PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE
(PERIPH_BASE + 0x20000)
+#define TIM2_BASE
(APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE
(APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE
(APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE
(APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE
(APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE
(APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE
(APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE
(APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE
(APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE
(APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE
(APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE
(APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE
(APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE
(APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE
(APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE
(APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE
(APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE
(APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE
(APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE
(APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE
(APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE
(APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE
(APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE
(APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE
(APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE
(APB1PERIPH_BASE + 0x7800)
+#define AFIO_BASE
(APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE
(APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE
(APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE
(APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE
(APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE
(APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE
(APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE
(APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE
(APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE
(APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE
(APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE
(APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE
(APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE
(APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE
(APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE
(APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE
(APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE
(APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE
(APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE
(APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE
(APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE
(APB2PERIPH_BASE + 0x5400)
+#define SDIO_BASE
(PERIPH_BASE + 0x18000)
+#define DMA1_BASE
(AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE
(AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE
(AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE
(AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE
(AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE
(AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE
(AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE
(AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE
(AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE
(AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE
(AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE
(AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE
(AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE
(AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE
(AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE
(AHBPERIPH_BASE + 0x3000)
+#define FLASH_R_BASE
(AHBPERIPH_BASE + 0x2000) /*!& Flash registers base address */
+#define OB_BASE
((uint32_t)0x1FFFF800)
/*!& Flash Option Bytes base address */
+#define ETH_BASE
(AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE
(ETH_BASE)
+#define ETH_MMC_BASE
(ETH_BASE + 0x0100)
+#define ETH_PTP_BASE
(ETH_BASE + 0x0700)
+#define ETH_DMA_BASE
(ETH_BASE + 0x1000)
+#define FSMC_Bank1_R_BASE
(FSMC_R_BASE + 0x0000) /*!& FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE
(FSMC_R_BASE + 0x0104) /*!& FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE
(FSMC_R_BASE + 0x0060) /*!& FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE
(FSMC_R_BASE + 0x0080) /*!& FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE
(FSMC_R_BASE + 0x00A0) /*!& FSMC Bank4 registers base address */
+#define DBGMCU_BASE
((uint32_t)0xE0042000) /*!& Debug MCU registers base address */
+/** @addtogroup Peripheral_declaration
+#define TIM2
((TIM_TypeDef *) TIM2_BASE)
+#define TIM3
((TIM_TypeDef *) TIM3_BASE)
+#define TIM4
((TIM_TypeDef *) TIM4_BASE)
+#define TIM5
((TIM_TypeDef *) TIM5_BASE)
+#define TIM6
((TIM_TypeDef *) TIM6_BASE)
+#define TIM7
((TIM_TypeDef *) TIM7_BASE)
+#define TIM12
((TIM_TypeDef *) TIM12_BASE)
+#define TIM13
((TIM_TypeDef *) TIM13_BASE)
+#define TIM14
((TIM_TypeDef *) TIM14_BASE)
+#define RTC
((RTC_TypeDef *) RTC_BASE)
+#define WWDG
((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG
((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2
((SPI_TypeDef *) SPI2_BASE)
+#define SPI3
((SPI_TypeDef *) SPI3_BASE)
+#define USART2
((USART_TypeDef *) USART2_BASE)
+#define USART3
((USART_TypeDef *) USART3_BASE)
+#define UART4
((USART_TypeDef *) UART4_BASE)
+#define UART5
((USART_TypeDef *) UART5_BASE)
+#define I2C1
((I2C_TypeDef *) I2C1_BASE)
+#define I2C2
((I2C_TypeDef *) I2C2_BASE)
+#define CAN1
((CAN_TypeDef *) CAN1_BASE)
+#define CAN2
((CAN_TypeDef *) CAN2_BASE)
+#define BKP
((BKP_TypeDef *) BKP_BASE)
+#define PWR
((PWR_TypeDef *) PWR_BASE)
+#define DAC
((DAC_TypeDef *) DAC_BASE)
+#define CEC
((CEC_TypeDef *) CEC_BASE)
+#define AFIO
((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI
((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA
((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB
((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC
((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD
((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE
((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF
((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG
((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1
((ADC_TypeDef *) ADC1_BASE)
+#define ADC2
((ADC_TypeDef *) ADC2_BASE)
+#define TIM1
((TIM_TypeDef *) TIM1_BASE)
+#define SPI1
((SPI_TypeDef *) SPI1_BASE)
+#define TIM8
((TIM_TypeDef *) TIM8_BASE)
+#define USART1
((USART_TypeDef *) USART1_BASE)
+#define ADC3
((ADC_TypeDef *) ADC3_BASE)
+#define TIM15
((TIM_TypeDef *) TIM15_BASE)
+#define TIM16
((TIM_TypeDef *) TIM16_BASE)
+#define TIM17
((TIM_TypeDef *) TIM17_BASE)
+#define TIM9
((TIM_TypeDef *) TIM9_BASE)
+#define TIM10
((TIM_TypeDef *) TIM10_BASE)
+#define TIM11
((TIM_TypeDef *) TIM11_BASE)
+#define SDIO
((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1
((DMA_TypeDef *) DMA1_BASE)
+#define DMA2
((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1
((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2
((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3
((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4
((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5
((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6
((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7
((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1
((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2
((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3
((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4
((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5
((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC
((RCC_TypeDef *) RCC_BASE)
+#define CRC
((CRC_TypeDef *) CRC_BASE)
+#define FLASH
((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB
((OB_TypeDef *) OB_BASE)
+#define ETH
((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1
((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E
((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2
((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3
((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4
((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU
((DBGMCU_TypeDef *) DBGMCU_BASE)
+/** @addtogroup Exported_constants
/** @addtogroup Peripheral_Registers_Bits_Definition
+/******************************************************************************/
Peripheral Registers_Bits_Definition
+/******************************************************************************/
+/******************************************************************************/
CRC calculation unit
+/******************************************************************************/
+/*******************
Bit definition for CRC_DR register
*********************/
((uint32_t)0xFFFFFFFF) /*!& Data register bits */
+/*******************
Bit definition for CRC_IDR register
********************/
CRC_IDR_IDR
((uint8_t)0xFF)
/*!& General-purpose 8-bit data register bits */
+/********************
Bit definition for CRC_CR register
********************/
CRC_CR_RESET
((uint8_t)0x01)
/*!& RESET bit */
+/******************************************************************************/
Power Control
+/******************************************************************************/
+/********************
Bit definition for PWR_CR register
********************/
PWR_CR_LPDS
((uint16_t)0x0001)
/*!& Low-Power Deepsleep */
PWR_CR_PDDS
((uint16_t)0x0002)
/*!& Power Down Deepsleep */
PWR_CR_CWUF
((uint16_t)0x0004)
/*!& Clear Wakeup Flag */
PWR_CR_CSBF
((uint16_t)0x0008)
/*!& Clear Standby Flag */
PWR_CR_PVDE
((uint16_t)0x0010)
/*!& Power Voltage Detector Enable */
PWR_CR_PLS
((uint16_t)0x00E0)
/*!& PLS[2:0] bits (PVD Level Selection) */
PWR_CR_PLS_0
((uint16_t)0x0020)
/*!& Bit 0 */
PWR_CR_PLS_1
((uint16_t)0x0040)
/*!& Bit 1 */
PWR_CR_PLS_2
((uint16_t)0x0080)
/*!& Bit 2 */
+/*!& PVD level configuration */
PWR_CR_PLS_2V2
((uint16_t)0x0000)
/*!& PVD level 2.2V */
PWR_CR_PLS_2V3
((uint16_t)0x0020)
/*!& PVD level 2.3V */
PWR_CR_PLS_2V4
((uint16_t)0x0040)
/*!& PVD level 2.4V */
PWR_CR_PLS_2V5
((uint16_t)0x0060)
/*!& PVD level 2.5V */
PWR_CR_PLS_2V6
((uint16_t)0x0080)
/*!& PVD level 2.6V */
PWR_CR_PLS_2V7
((uint16_t)0x00A0)
/*!& PVD level 2.7V */
PWR_CR_PLS_2V8
((uint16_t)0x00C0)
/*!& PVD level 2.8V */
PWR_CR_PLS_2V9
((uint16_t)0x00E0)
/*!& PVD level 2.9V */
PWR_CR_DBP
((uint16_t)0x0100)
/*!& Disable Backup Domain write protection */
+/*******************
Bit definition for PWR_CSR register
********************/
PWR_CSR_WUF
((uint16_t)0x0001)
/*!& Wakeup Flag */
PWR_CSR_SBF
((uint16_t)0x0002)
/*!& Standby Flag */
PWR_CSR_PVDO
((uint16_t)0x0004)
/*!& PVD Output */
PWR_CSR_EWUP
((uint16_t)0x0100)
/*!& Enable WKUP pin */
+/******************************************************************************/
Backup registers
+/******************************************************************************/
+/*******************
Bit definition for BKP_DR1 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR2 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR3 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR4 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR5 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR6 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR7 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR8 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR9 register
********************/
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR10 register
*******************/
BKP_DR10_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR11 register
*******************/
BKP_DR11_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR12 register
*******************/
BKP_DR12_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR13 register
*******************/
BKP_DR13_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR14 register
*******************/
BKP_DR14_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR15 register
*******************/
BKP_DR15_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR16 register
*******************/
BKP_DR16_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR17 register
*******************/
BKP_DR17_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/******************
Bit definition for BKP_DR18 register
********************/
BKP_DR18_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR19 register
*******************/
BKP_DR19_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR20 register
*******************/
BKP_DR20_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR21 register
*******************/
BKP_DR21_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR22 register
*******************/
BKP_DR22_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR23 register
*******************/
BKP_DR23_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR24 register
*******************/
BKP_DR24_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR25 register
*******************/
BKP_DR25_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR26 register
*******************/
BKP_DR26_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR27 register
*******************/
BKP_DR27_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR28 register
*******************/
BKP_DR28_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR29 register
*******************/
BKP_DR29_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR30 register
*******************/
BKP_DR30_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR31 register
*******************/
BKP_DR31_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR32 register
*******************/
BKP_DR32_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR33 register
*******************/
BKP_DR33_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR34 register
*******************/
BKP_DR34_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR35 register
*******************/
BKP_DR35_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR36 register
*******************/
BKP_DR36_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR37 register
*******************/
BKP_DR37_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR38 register
*******************/
BKP_DR38_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR39 register
*******************/
BKP_DR39_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR40 register
*******************/
BKP_DR40_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR41 register
*******************/
BKP_DR41_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/*******************
Bit definition for BKP_DR42 register
*******************/
BKP_DR42_D
((uint16_t)0xFFFF)
/*!& Backup data */
+/******************
Bit definition for BKP_RTCCR register
*******************/
BKP_RTCCR_CAL
((uint16_t)0x007F)
/*!& Calibration value */
BKP_RTCCR_CCO
((uint16_t)0x0080)
/*!& Calibration Clock Output */
BKP_RTCCR_ASOE
((uint16_t)0x0100)
/*!& Alarm or Second Output Enable */
BKP_RTCCR_ASOS
((uint16_t)0x0200)
/*!& Alarm or Second Output Selection */
+/********************
Bit definition for BKP_CR register
********************/
BKP_CR_TPE
((uint8_t)0x01)
/*!& TAMPER pin enable */
BKP_CR_TPAL
((uint8_t)0x02)
/*!& TAMPER pin active level */
+/*******************
Bit definition for BKP_CSR register
********************/
BKP_CSR_CTE
((uint16_t)0x0001)
/*!& Clear Tamper event */
BKP_CSR_CTI
((uint16_t)0x0002)
/*!& Clear Tamper Interrupt */
BKP_CSR_TPIE
((uint16_t)0x0004)
/*!& TAMPER Pin interrupt enable */
BKP_CSR_TEF
((uint16_t)0x0100)
/*!& Tamper Event Flag */
BKP_CSR_TIF
((uint16_t)0x0200)
/*!& Tamper Interrupt Flag */
+/******************************************************************************/
Reset and Clock Control
+/******************************************************************************/
+/********************
Bit definition for RCC_CR register
********************/
RCC_CR_HSION
((uint32_t)0x)
/*!& Internal High Speed clock enable */
RCC_CR_HSIRDY
((uint32_t)0x)
/*!& Internal High Speed clock ready flag */
RCC_CR_HSITRIM
((uint32_t)0x)
/*!& Internal High Speed clock trimming */
RCC_CR_HSICAL
((uint32_t)0x0000FF00)
/*!& Internal High Speed clock Calibration */
RCC_CR_HSEON
((uint32_t)0x)
/*!& External High Speed clock enable */
RCC_CR_HSERDY
((uint32_t)0x)
/*!& External High Speed clock ready flag */
RCC_CR_HSEBYP
((uint32_t)0x)
/*!& External High Speed clock Bypass */
RCC_CR_CSSON
((uint32_t)0x)
/*!& Clock Security System enable */
RCC_CR_PLLON
((uint32_t)0x)
/*!& PLL enable */
RCC_CR_PLLRDY
((uint32_t)0x)
/*!& PLL clock ready flag */
+#ifdef STM32F10X_CL
RCC_CR_PLL2ON
((uint32_t)0x)
/*!& PLL2 enable */
RCC_CR_PLL2RDY
((uint32_t)0x)
/*!& PLL2 clock ready flag */
RCC_CR_PLL3ON
((uint32_t)0x)
/*!& PLL3 enable */
RCC_CR_PLL3RDY
((uint32_t)0x)
/*!& PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+/*******************
Bit definition for RCC_CFGR register
*******************/
+/*!& SW configuration */
RCC_CFGR_SW
((uint32_t)0x)
/*!& SW[1:0] bits (System clock Switch) */
RCC_CFGR_SW_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_SW_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_SW_HSI
((uint32_t)0x)
/*!& HSI selected as system clock */
RCC_CFGR_SW_HSE
((uint32_t)0x)
/*!& HSE selected as system clock */
RCC_CFGR_SW_PLL
((uint32_t)0x)
/*!& PLL selected as system clock */
+/*!& SWS configuration */
RCC_CFGR_SWS
((uint32_t)0x0000000C)
/*!& SWS[1:0] bits (System Clock Switch Status) */
RCC_CFGR_SWS_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_SWS_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_SWS_HSI
((uint32_t)0x)
/*!& HSI oscillator used as system clock */
RCC_CFGR_SWS_HSE
((uint32_t)0x)
/*!& HSE oscillator used as system clock */
RCC_CFGR_SWS_PLL
((uint32_t)0x)
/*!& PLL used as system clock */
+/*!& HPRE configuration */
RCC_CFGR_HPRE
((uint32_t)0x)
/*!& HPRE[3:0] bits (AHB prescaler) */
RCC_CFGR_HPRE_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_HPRE_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_HPRE_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_HPRE_3
((uint32_t)0x)
/*!& Bit 3 */
RCC_CFGR_HPRE_DIV1
((uint32_t)0x)
/*!& SYSCLK not divided */
RCC_CFGR_HPRE_DIV2
((uint32_t)0x)
/*!& SYSCLK divided by 2 */
RCC_CFGR_HPRE_DIV4
((uint32_t)0x)
/*!& SYSCLK divided by 4 */
RCC_CFGR_HPRE_DIV8
((uint32_t)0x)
/*!& SYSCLK divided by 8 */
RCC_CFGR_HPRE_DIV16
((uint32_t)0x)
/*!& SYSCLK divided by 16 */
RCC_CFGR_HPRE_DIV64
((uint32_t)0x)
/*!& SYSCLK divided by 64 */
RCC_CFGR_HPRE_DIV128
((uint32_t)0x)
/*!& SYSCLK divided by 128 */
RCC_CFGR_HPRE_DIV256
((uint32_t)0x)
/*!& SYSCLK divided by 256 */
RCC_CFGR_HPRE_DIV512
((uint32_t)0x)
/*!& SYSCLK divided by 512 */
+/*!& PPRE1 configuration */
RCC_CFGR_PPRE1
((uint32_t)0x)
/*!& PRE1[2:0] bits (APB1 prescaler) */
RCC_CFGR_PPRE1_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_PPRE1_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_PPRE1_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_PPRE1_DIV1
((uint32_t)0x)
/*!& HCLK not divided */
RCC_CFGR_PPRE1_DIV2
((uint32_t)0x)
/*!& HCLK divided by 2 */
RCC_CFGR_PPRE1_DIV4
((uint32_t)0x)
/*!& HCLK divided by 4 */
RCC_CFGR_PPRE1_DIV8
((uint32_t)0x)
/*!& HCLK divided by 8 */
RCC_CFGR_PPRE1_DIV16
((uint32_t)0x)
/*!& HCLK divided by 16 */
+/*!& PPRE2 configuration */
RCC_CFGR_PPRE2
((uint32_t)0x)
/*!& PRE2[2:0] bits (APB2 prescaler) */
RCC_CFGR_PPRE2_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_PPRE2_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_PPRE2_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_PPRE2_DIV1
((uint32_t)0x)
/*!& HCLK not divided */
RCC_CFGR_PPRE2_DIV2
((uint32_t)0x)
/*!& HCLK divided by 2 */
RCC_CFGR_PPRE2_DIV4
((uint32_t)0x)
/*!& HCLK divided by 4 */
RCC_CFGR_PPRE2_DIV8
((uint32_t)0x)
/*!& HCLK divided by 8 */
RCC_CFGR_PPRE2_DIV16
((uint32_t)0x)
/*!& HCLK divided by 16 */
+/*!& ADCPPRE configuration */
RCC_CFGR_ADCPRE
((uint32_t)0x)
/*!& ADCPRE[1:0] bits (ADC prescaler) */
RCC_CFGR_ADCPRE_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_ADCPRE_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_ADCPRE_DIV2
((uint32_t)0x)
/*!& PCLK2 divided by 2 */
RCC_CFGR_ADCPRE_DIV4
((uint32_t)0x)
/*!& PCLK2 divided by 4 */
RCC_CFGR_ADCPRE_DIV6
((uint32_t)0x)
/*!& PCLK2 divided by 6 */
RCC_CFGR_ADCPRE_DIV8
((uint32_t)0x)
/*!& PCLK2 divided by 8 */
RCC_CFGR_PLLSRC
((uint32_t)0x)
/*!& PLL entry clock source */
RCC_CFGR_PLLXTPRE
((uint32_t)0x)
/*!& HSE divider for PLL entry */
+/*!& PLLMUL configuration */
RCC_CFGR_PLLMULL
((uint32_t)0x003C0000)
/*!& PLLMUL[3:0] bits (PLL multiplication factor) */
RCC_CFGR_PLLMULL_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_PLLMULL_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_PLLMULL_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_PLLMULL_3
((uint32_t)0x)
/*!& Bit 3 */
+#ifdef STM32F10X_CL
RCC_CFGR_PLLSRC_HSI_Div2
((uint32_t)0x)
/*!& HSI clock divided by 2 selected as PLL entry clock source */
RCC_CFGR_PLLSRC_PREDIV1
((uint32_t)0x)
/*!& PREDIV1 clock selected as PLL entry clock source */
RCC_CFGR_PLLXTPRE_PREDIV1
((uint32_t)0x)
/*!& PREDIV1 clock not divided for PLL entry */
RCC_CFGR_PLLXTPRE_PREDIV1_Div2
((uint32_t)0x)
/*!& PREDIV1 clock divided by 2 for PLL entry */
RCC_CFGR_PLLMULL4
((uint32_t)0x)
/*!& PLL input clock * 4 */
RCC_CFGR_PLLMULL5
((uint32_t)0x000C0000)
/*!& PLL input clock * 5 */
RCC_CFGR_PLLMULL6
((uint32_t)0x)
/*!& PLL input clock * 6 */
RCC_CFGR_PLLMULL7
((uint32_t)0x)
/*!& PLL input clock * 7 */
RCC_CFGR_PLLMULL8
((uint32_t)0x)
/*!& PLL input clock * 8 */
RCC_CFGR_PLLMULL9
((uint32_t)0x001C0000)
/*!& PLL input clock * 9 */
RCC_CFGR_PLLMULL6_5
((uint32_t)0x)
/*!& PLL input clock * 6.5 */
RCC_CFGR_OTGFSPRE
((uint32_t)0x)
/*!& USB OTG FS prescaler */
+/*!& MCO configuration */
RCC_CFGR_MCO
((uint32_t)0x0F000000)
/*!& MCO[3:0] bits (Microcontroller Clock Output) */
RCC_CFGR_MCO_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_MCO_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_MCO_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_MCO_3
((uint32_t)0x)
/*!& Bit 3 */
RCC_CFGR_MCO_NOCLOCK
((uint32_t)0x)
/*!& No clock */
RCC_CFGR_MCO_SYSCLK
((uint32_t)0x)
/*!& System clock selected as MCO source */
RCC_CFGR_MCO_HSI
((uint32_t)0x)
/*!& HSI clock selected as MCO source */
RCC_CFGR_MCO_HSE
((uint32_t)0x)
/*!& HSE clock selected as MCO source */
RCC_CFGR_MCO_PLLCLK_Div2
((uint32_t)0x)
/*!& PLL clock divided by 2 selected as MCO source */
RCC_CFGR_MCO_PLL2CLK
((uint32_t)0x)
/*!& PLL2 clock selected as MCO source*/
RCC_CFGR_MCO_PLL3CLK_Div2
((uint32_t)0x)
/*!& PLL3 clock divided by 2 selected as MCO source*/
RCC_CFGR_MCO_Ext_HSE
((uint32_t)0x0A000000)
/*!& XT1 external 3-25 MHz oscillator clock selected as MCO source */
RCC_CFGR_MCO_PLL3CLK
((uint32_t)0x0B000000)
/*!& PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
RCC_CFGR_PLLSRC_HSI_Div2
((uint32_t)0x)
/*!& HSI clock divided by 2 selected as PLL entry clock source */
RCC_CFGR_PLLSRC_PREDIV1
((uint32_t)0x)
/*!& PREDIV1 clock selected as PLL entry clock source */
RCC_CFGR_PLLXTPRE_PREDIV1
((uint32_t)0x)
/*!& PREDIV1 clock not divided for PLL entry */
RCC_CFGR_PLLXTPRE_PREDIV1_Div2
((uint32_t)0x)
/*!& PREDIV1 clock divided by 2 for PLL entry */
RCC_CFGR_PLLMULL2
((uint32_t)0x)
/*!& PLL input clock*2 */
RCC_CFGR_PLLMULL3
((uint32_t)0x)
/*!& PLL input clock*3 */
RCC_CFGR_PLLMULL4
((uint32_t)0x)
/*!& PLL input clock*4 */
RCC_CFGR_PLLMULL5
((uint32_t)0x000C0000)
/*!& PLL input clock*5 */
RCC_CFGR_PLLMULL6
((uint32_t)0x)
/*!& PLL input clock*6 */
RCC_CFGR_PLLMULL7
((uint32_t)0x)
/*!& PLL input clock*7 */
RCC_CFGR_PLLMULL8
((uint32_t)0x)
/*!& PLL input clock*8 */
RCC_CFGR_PLLMULL9
((uint32_t)0x001C0000)
/*!& PLL input clock*9 */
RCC_CFGR_PLLMULL10
((uint32_t)0x)
/*!& PLL input clock10 */
RCC_CFGR_PLLMULL11
((uint32_t)0x)
/*!& PLL input clock*11 */
RCC_CFGR_PLLMULL12
((uint32_t)0x)
/*!& PLL input clock*12 */
RCC_CFGR_PLLMULL13
((uint32_t)0x002C0000)
/*!& PLL input clock*13 */
RCC_CFGR_PLLMULL14
((uint32_t)0x)
/*!& PLL input clock*14 */
RCC_CFGR_PLLMULL15
((uint32_t)0x)
/*!& PLL input clock*15 */
RCC_CFGR_PLLMULL16
((uint32_t)0x)
/*!& PLL input clock*16 */
+/*!& MCO configuration */
RCC_CFGR_MCO
((uint32_t)0x)
/*!& MCO[2:0] bits (Microcontroller Clock Output) */
RCC_CFGR_MCO_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_MCO_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_MCO_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_MCO_NOCLOCK
((uint32_t)0x)
/*!& No clock */
RCC_CFGR_MCO_SYSCLK
((uint32_t)0x)
/*!& System clock selected as MCO source */
RCC_CFGR_MCO_HSI
((uint32_t)0x)
/*!& HSI clock selected as MCO source */
RCC_CFGR_MCO_HSE
((uint32_t)0x)
/*!& HSE clock selected as MCO source
RCC_CFGR_MCO_PLL
((uint32_t)0x)
/*!& PLL clock divided by 2 selected as MCO source */
RCC_CFGR_PLLSRC_HSI_Div2
((uint32_t)0x)
/*!& HSI clock divided by 2 selected as PLL entry clock source */
RCC_CFGR_PLLSRC_HSE
((uint32_t)0x)
/*!& HSE clock selected as PLL entry clock source */
RCC_CFGR_PLLXTPRE_HSE
((uint32_t)0x)
/*!& HSE clock not divided for PLL entry */
RCC_CFGR_PLLXTPRE_HSE_Div2
((uint32_t)0x)
/*!& HSE clock divided by 2 for PLL entry */
RCC_CFGR_PLLMULL2
((uint32_t)0x)
/*!& PLL input clock*2 */
RCC_CFGR_PLLMULL3
((uint32_t)0x)
/*!& PLL input clock*3 */
RCC_CFGR_PLLMULL4
((uint32_t)0x)
/*!& PLL input clock*4 */
RCC_CFGR_PLLMULL5
((uint32_t)0x000C0000)
/*!& PLL input clock*5 */
RCC_CFGR_PLLMULL6
((uint32_t)0x)
/*!& PLL input clock*6 */
RCC_CFGR_PLLMULL7
((uint32_t)0x)
/*!& PLL input clock*7 */
RCC_CFGR_PLLMULL8
((uint32_t)0x)
/*!& PLL input clock*8 */
RCC_CFGR_PLLMULL9
((uint32_t)0x001C0000)
/*!& PLL input clock*9 */
RCC_CFGR_PLLMULL10
((uint32_t)0x)
/*!& PLL input clock10 */
RCC_CFGR_PLLMULL11
((uint32_t)0x)
/*!& PLL input clock*11 */
RCC_CFGR_PLLMULL12
((uint32_t)0x)
/*!& PLL input clock*12 */
RCC_CFGR_PLLMULL13
((uint32_t)0x002C0000)
/*!& PLL input clock*13 */
RCC_CFGR_PLLMULL14
((uint32_t)0x)
/*!& PLL input clock*14 */
RCC_CFGR_PLLMULL15
((uint32_t)0x)
/*!& PLL input clock*15 */
RCC_CFGR_PLLMULL16
((uint32_t)0x)
/*!& PLL input clock*16 */
RCC_CFGR_USBPRE
((uint32_t)0x)
/*!& USB Device prescaler */
+/*!& MCO configuration */
RCC_CFGR_MCO
((uint32_t)0x)
/*!& MCO[2:0] bits (Microcontroller Clock Output) */
RCC_CFGR_MCO_0
((uint32_t)0x)
/*!& Bit 0 */
RCC_CFGR_MCO_1
((uint32_t)0x)
/*!& Bit 1 */
RCC_CFGR_MCO_2
((uint32_t)0x)
/*!& Bit 2 */
RCC_CFGR_MCO_NOCLOCK
((uint32_t)0x)
/*!& No clock */
RCC_CFGR_MCO_SYSCLK
((uint32_t)0x)
/*!& System clock selected as MCO source */
RCC_CFGR_MCO_HSI
((uint32_t)0x)
/*!& HSI clock selected as MCO source */
RCC_CFGR_MCO_HSE
((uint32_t)0x)
/*!& HSE clock selected as MCO source
RCC_CFGR_MCO_PLL
((uint32_t)0x)
/*!& PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+/*!&******************
Bit definition for RCC_CIR register
********************/
RCC_CIR_LSIRDYF
((uint32_t)0x)
/*!& LSI Ready Interrupt flag */
RCC_CIR_LSERDYF
((uint32_t)0x)
/*!& LSE Ready Interrupt flag */
RCC_CIR_HSIRDYF
((uint32_t)0x)
/*!& HSI Ready Interrupt flag */
RCC_CIR_HSERDYF
((uint32_t)0x)
/*!& HSE Ready Interrupt flag */
RCC_CIR_PLLRDYF
((uint32_t)0x)
/*!& PLL Ready Interrupt flag */
RCC_CIR_CSSF
((uint32_t)0x)
/*!& Clock Security System Interrupt flag */
RCC_CIR_LSIRDYIE
((uint32_t)0x)
/*!& LSI Ready Interrupt Enable */
RCC_CIR_LSERDYIE
((uint32_t)0x)
/*!& LSE Ready Interrupt Enable */
RCC_CIR_HSIRDYIE
((uint32_t)0x)
/*!& HSI Ready Interrupt Enable */
RCC_CIR_HSERDYIE
((uint32_t)0x)
/*!& HSE Ready Interrupt Enable */
RCC_CIR_PLLRDYIE
((uint32_t)0x)
/*!& PLL Ready Interrupt Enable */
RCC_CIR_LSIRDYC
((uint32_t)0x)
/*!& LSI Ready Interrupt Clear */
RCC_CIR_LSERDYC
((uint32_t)0x)
/*!& LSE Ready Interrupt Clear */
RCC_CIR_HSIRDYC
((uint32_t)0x)
/*!& HSI Ready Interrupt Clear */
RCC_CIR_HSERDYC
((uint32_t)0x)
/*!& HSE Ready Interrupt Clear */
RCC_CIR_PLLRDYC
((uint32_t)0x)
/*!& PLL Ready Interrupt Clear */
RCC_CIR_CSSC
((uint32_t)0x)
/*!& Clock Security System Interrupt Clear */
+#ifdef STM32F10X_CL
RCC_CIR_PLL2RDYF
((uint32_t)0x)
/*!& PLL2 Ready Interrupt flag */
RCC_CIR_PLL3RDYF
((uint32_t)0x)
/*!& PLL3 Ready Interrupt flag */
RCC_CIR_PLL2RDYIE
((uint32_t)0x)
/*!& PLL2 Ready Interrupt Enable */
RCC_CIR_PLL3RDYIE
((uint32_t)0x)
/*!& PLL3 Ready Interrupt Enable */
RCC_CIR_PLL2RDYC
((uint32_t)0x)
/*!& PLL2 Ready Interrupt Clear */
RCC_CIR_PLL3RDYC
((uint32_t)0x)
/*!& PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+/*****************
Bit definition for RCC_APB2RSTR register
*****************/
RCC_APB2RSTR_AFIORST
((uint32_t)0x)
/*!& Alternate Function I/O reset */
RCC_APB2RSTR_IOPARST
((uint32_t)0x)
/*!& I/O port A reset */
RCC_APB2RSTR_IOPBRST
((uint32_t)0x)
/*!& I/O port B reset */
RCC_APB2RSTR_IOPCRST
((uint32_t)0x)
/*!& I/O port C reset */
RCC_APB2RSTR_IOPDRST
((uint32_t)0x)
/*!& I/O port D reset */
RCC_APB2RSTR_ADC1RST
((uint32_t)0x)
/*!& ADC 1 interface reset */
+#if !defined (STM32F10X_LD_VL) && !de