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贴数:2&分页:好多问题发信人: techquest (好多问题), 信区: WindowsDriverDev
标&&题: 关于串口硬件流控的一些疑问
发信站: 水木社区 (Wed Dec 23 00:05:31 2009), 站内 && 现在有一个小ARM的板子，运行WINCE系统，通过串口和外接的GPS通信。
目前没有采用任何流控机制，但是发现在系统繁忙的时候，UART经常丢失数据，应该是FIFO溢出了。
现在想通过硬件握手信号来进行流控。
查阅了MSDN，看得不是很明白。SetCommState中的DCB参数中，有两个关于流控的设置。 && 一个是fDtrControl，看名字来看，应该ARM(DTE)告诉GPS(DCE)，说ARM已经准备好了，可以传输数据了。
这个看起来似乎是对GPS-&ARM方向的数据进行流控。 && 另一个是fRtsControl，这个看起来更像是ARM-&GPS方向的流控。
但是帮助中说，该脚在输入缓冲区占据3/4以上的时候设置为低，在低于1/2的时候设置为高。
这样理解起来更像是GPS-&ARM方向的流控。但是按照我对RTS的理解，RTS应该是请求向GPS发送数据才对啊。 && 究竟怎样理解才对呢？是不是上面两种方法都可以实现GPS-&ARM方向的流控？
非常感谢！ && -- && ※ 来源:·水木社区 newsmth.net·[FROM: 117.136.12.*]
塑料袋子在飞翔发信人: xiaopiqiu (塑料袋子在飞翔), 信区: WindowsDriverDev
标&&题: Re: 关于串口硬件流控的一些疑问
发信站: 水木社区 (Thu May&&6 13:19:40 2010), 站内 && 两种方式都可以的，DTR方式和RTS流控方式，
流控的实现是在 串口驱动里边要实现的，当数据到达一定量3/4时，就会发RTS信号，告诉对方现在FIFO已经不能再接受数据了，当小到一定量时1/4，将该信号解除， && 问题是你先要确认硬件除了 RX,TX,GND外，是否还有RTS，CTS信号与GPS相连。
还有你的GPS模块是否支持流控 && 【 在 techquest (好多问题) 的大作中提到: 】
: 现在有一个小ARM的板子，运行WINCE系统，通过串口和外接的GPS通信。
: 目前没有采用任何流控机制，但是发现在系统繁忙的时候，UART经常丢失数据，应该是FIFO溢出了。
: 现在想通过硬件握手信号来进行流控。
: ...................
&& -- && ※ 来源:·水木社区 ·[FROM: 124.207.145.*]
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&&& S3C6410 串口 UARTx 的时钟源比较复杂，具体应用时，可以通过寄存器 UCONn 来选择时钟的来源。& & & & PCLK 由 APLL(同步模式时)分频得到，或由 MPLL(异步模式时)分频得到；& &&& EXT_UCLK0 clock is external clock.(XpwmECLK PAD input)，一般很少用；&&& EXT_UCLK1 clock is generated clock by SYSCON. SYSCON generates EXT_UCLK1 for dividing EPLL or MPLL output.&&& &&& 接下来我们看看 SYSCON 是如何产生 EXT_UCLK1 的？& &
& & & 上图的 CLKUART 其实就是 EXT_UCLK1，它和 PCLK 一样都可以为串口 IP 模块提供时钟源，即串口模块的波特率可以由该时钟源分频得到。既然这样为何不直接使用 PCLK 作为时钟源？这是因为 PCLK 最大可以产生的波特率是 115200bps，但是有时候用户可能需要更大的波特率，这就不得不用到 EXT_UCLK0 或 EXT_UCLK1。&&& MUXuart 开关控制着分频器之前的时钟来源，它由寄存器 CLK_SRC bit[13] 来设置。CLK_SRC&&& &&& DIVIDER 是将输入的时钟进行分频，最终得到 CLKUART(EXT_UCLK1),它由寄存器 CLK_DIV2 bit[19:16] 来设置。CLK_DIV2& & && &&& 通过上述的分析我们知道，串口模块可以通过 UCONn 寄存器的 bit[11:10] 来选择时钟源为 PCLK 或 EXT_UCLK1。但是千万要注意，这仅仅是选择！它只是把 PCLK/EXT_UCLK1 到串口 IP 模块输入时钟(对于一个含有时序逻辑的 IP 模块，一定需要一个输入时钟作为基准)的这条路打开，这并不意味着 PCLK/EXT_UCLK1(这里只是泛泛地讲PCLK，确切来说应该叫做 PCLK_UARTx) 一定存在。这就好比说，我们打开了水龙头，但是这并不能保证一定会有水流出来，因为水泵都没有工作。&&& S3C6410 通过 PCLK_GATE 和 SCLK_GATE 来控制这些开关。PCLK_GATE& & && SCLK_GATE&&& &&& 注意：当选择 PCLK 作为串口的时钟源时，寄存器相应位应该设置成什么和上一个状态有关系。When you want to change EXT_UCLK0 to PCLK for UART baudrate , clock selection field must be set to 2’b00.But, when you want to change EXT_UCLK1 to PCLK for UART baudrate , clock selection field must be set to 2’b10.&&& Tiny6410 提供的 u-boot 将串口的时钟源设为 EXT_UCLK1，因此当我们用 u-boot 调试裸机程序的时候，如果需要自己初始化串口应特别注意，可以按下面的示例代码初始化串口：void uart_init(void){&&& GPACON &= ~0&&& /* 选择引脚功能 */&&& GPACON |= 0x22;&&& &&& ULCON0 = 0x3;& &&& &&& /* 数据位:8, 无较验, 停止位: 1, 8n1 */&&& UCON0& = 0x805;& &&&&& /* 使能UART发送、接收& 选择时钟源*/&&& UFCON0 = 0x01; &&& &&& /* FIFO ENABLE */&&& UMCON0 = 0;&&& &&& /* DIV_VAL = (PCLK / (bps x 16 ) ) - 1 &&& &* bps = 115200&&& &* DIV_VAL = ( / (115200 x 16 ) ) - 1 = 35.08&&&&&& &&& &*/&&& UBRDIV0&& = 35;&&& UDIVSLOT0 = 0x1;}补充：Tiny6410 提供的 u-boot 开启了 MMU(我是不知道它为何这么做???)，因此使用 u-boot 下载(tftp/nfs)裸机程序到内存时，地址就不能简单地使用原来的内存地址 0xx6fffffff，应该使用映射后的地址。u-boot 里面使用的映射关系比较简单，地址 0x 映射到 0xc0000000(对于其他地址都存在线性关系)，另外在源代码的开头要关闭 MMU。&&&&&&&&&&&&&&&&&&&&&& ——忠于梦想 勇于实践&&& linux_xpj@opencores.org
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给主人留下些什么吧！~~
PCLK_GATE和SCLK_GATE都默认为UART选通，那么UART究竟是选PCLK作为时钟源，还是选特殊时钟作为时钟源？
&&博主威武啊~
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STM32串口硬件流控
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在线时间0 小时
昨天我搞了一下串口1的硬件流控,我在网上看到很多资料都是RTS和CTS的接法是交叉接的,可是好像接了都不行,不知道是不是程序问题还是接线的问题,原子哥,你有没有这样的例程,串口1的硬件流控的程序?
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金钱101932
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回复【楼主位】eircdd:
---------------------------------
我没实际用过。
你看串口资料就知道了，规定信号了的。
我是开源电子网站长，有关站务问题请与我联系。
正点原子STM32开发板购买店铺：
微信公众平台：正点原子
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在线时间0 小时
串口没有使用流控,数据有时会丢失,所以,我想搞一下硬件流控试试看,可是发现好像不太行,交叉接,对接好像就行,也就是RTS与RTS相接,CTS与CTS相接,可是网上很多资料都显示说是RTS与CTS相接,CTS和RTS相接,可我试了不行
GPIO_InitTypeDef&GPIO_InitS
USART_InitTypeDef&USART_InitS
/*&config&USART1&clock&*/
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1&|&RCC_APB2Periph_GPIOA,&ENABLE);
/*&USART1&mode&config&*/
USART_InitStructure.USART_BaudRate&=&9600;
USART_InitStructure.USART_WordLength&=&USART_WordLength_8b;
USART_InitStructure.USART_StopBits&=&USART_StopBits_1;
USART_InitStructure.USART_Parity&=&USART_Parity_No&;
USART_InitStructure.USART_HardwareFlowControl&=&USART_HardwareFlowControl_N
AFIO-&MAPR=(AFIO-&MAPR|AFIO_MAPR_CAN_REMAP_0|AFIO_MAPR_CAN_REMAP_1)&AFIO_MAPR_CAN_REMAP_0;
/*&USART1&GPIO&config&*/
/*&Configure&USART1&Tx&(PA.09)&as&alternate&function&push-pull&*/
GPIO_InitStructure.GPIO_Pin&=&GPIO_Pin_9&|&GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode&=&GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed&=&GPIO_Speed_50MHz;
GPIO_Init(GPIOA,&&GPIO_InitStructure);&&&&
/*&Configure&USART1&Rx&(PA.10)&as&input&floating&*/
GPIO_InitStructure.GPIO_Pin&=&GPIO_Pin_10&|&GPIO_Pin_11;
GPIO_InitStructure.GPIO_Mode&=&GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA,&&GPIO_InitStructure);
USART_InitStructure.USART_Mode&=&USART_Mode_Rx&|&USART_Mode_Tx;
USART_Init(USART1,&&USART_InitStructure);
//USART_ITConfig(USART1,&USART_IT_RXNE,&ENABLE);
USART_Cmd(USART1,&ENABLE);
这是我串口的初始化
如果有人搞过串口流控的帮忙指点一下,交流交流你的经验
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你这个不是配置不使用流控的吗，换成USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;试试呢？
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回复【4楼】xzp114:
---------------------------------
我问一下，关于流控是单纯程序上的，还是硬件上面也要改？
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[S3C6410]（10）
& & & &学习S3C6410最好的办法是从裸机程序开始，下面的程序是一个实现简单功能的S3C6410入门裸机程序。
& & & &s3c6410裸机程序：从uboot程序中提取的代码，包括初始化时钟、256M DDR、初始化串口等。
编译工具：arm-linux-gcc。
mini6410.h
#ifndef __CONFIG_H
#define __CONFIG_H
* High Level Configuration Options
* (easy to change)
#define CONFIG_S3C6410
/* in a SAMSUNG S3C6410 SoC */
#define CONFIG_S3C64XX
/* in a SAMSUNG S3C64XX Family
#define CONFIG_MINI6410
/* on a FriendlyARM MINI6410 Board */
#define MEMORY_BASE_ADDRESS 0x
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ
/* the SMDK6400 has 12MHz input clock */
//#define CONFIG_ENABLE_MMU
disable by gong
#ifdef CONFIG_ENABLE_MMU
#define virt_to_phys(x) virt_to_phy_smdk6410(x)
#define virt_to_phys(x) (x)
//#define CONFIG_MEMORY_UPPER_CODE
#undef CONFIG_USE_IRQ
/* we don't need IRQ/FIQ stuff */
//#define CONFIG_INCLUDE_TEST
//#define CONFIG_ZIMAGE_BOOT
//#define CONFIG_IMAGE_BOOT
#define BOARD_LATE_INIT
#define CONFIG_SETUP_MEMORY_TAGS
//#define CONFIG_CMDLINE_TAG
//#define CONFIG_INITRD_TAG
* Architecture magic and machine type
#define MACH_TYPE
#define UBOOT_MAGIC
(0x | MACH_TYPE)
/* Power Management is enabled */
//#define CONFIG_PM
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SKIP_RELOCATE_UBOOT
#undef CONFIG_USE_NOR_BOOT
* Size of malloc() pool
#define CFG_MALLOC_LEN
//#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_STACK_SIZE
* select serial console configuration
#define CONFIG_SERIAL1
1 /* we use SERIAL 1 on SMDK6400 */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define CFG_HZ
// at PCLK 66MHz
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { , 3, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
* The stack sizes are set up in start.S using the settings below
#define CONFIG_STACKSIZE 0x40000
/* regular stack 256KB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (2*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (2*1024) /* FIQ stack */
#define CONFIG_STACKSIZE_SVC (2*1024)
//#define CONFIG_CLK_800_133_66
//#define CONFIG_CLK_666_133_66
#define CONFIG_CLK_532_133_66
//#define CONFIG_CLK_400_133_66
//#define CONFIG_CLK_400_100_50
//#define CONFIG_CLK_OTHERS
#define CONFIG_CLKSRC_CLKUART
#define set_pll(mdiv, pdiv, sdiv) (1&&31 | mdiv&&16 | pdiv&&8 | sdiv)
#if defined(CONFIG_CLK_666_133_66) /* FIN 12MHz, Fout 666MHz */
#define APLL_MDIV 333
#define APLL_PDIV 3
#define APLL_SDIV 1
CONFIG_SYNC_MODE /* ASYNC MODE */
#elif defined(CONFIG_CLK_532_133_66) /* FIN 12MHz, Fout 532MHz */
#define APLL_MDIV 266
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_400_133_66) || defined(CONFIG_CLK_800_133_66) /* FIN 12MHz, Fout 800MHz */
#define APLL_MDIV 400
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_400_100_50) /* FIN 12MHz, Fout 400MHz */
#define APLL_MDIV 400
#define APLL_PDIV 3
#define APLL_SDIV 2
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_OTHERS)
/*If you have to use another value, please define pll value here*/
/* FIN 12MHz, Fout 532MHz */
#define APLL_MDIV 266
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#error &Not Support Fequency or Mode!! you have to setup right configuration.&
#define CONFIG_UART_66 /* default clock value of CLK_UART */
#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
/* prevent overflow */
#define Startup_APLL (CONFIG_SYS_CLK_FREQ/(APLL_PDIV&&APLL_SDIV)*APLL_MDIV)
/* fixed MPLL 533MHz */
#define MPLL_MDIV 266
#define MPLL_PDIV 3
#define MPLL_SDIV 1
#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
/* prevent overflow */
#define Startup_MPLL ((CONFIG_SYS_CLK_FREQ)/(MPLL_PDIV&&MPLL_SDIV)*MPLL_MDIV)
#if defined(CONFIG_CLK_800_133_66)
#define Startup_APLLdiv
#define Startup_HCLKx2div 2
#elif defined(CONFIG_CLK_400_133_66)
#define Startup_APLLdiv
#define Startup_HCLKx2div 2
#define Startup_APLLdiv
#define Startup_HCLKx2div 1
#define Startup_PCLKdiv
#define Startup_HCLKdiv
#define Startup_MPLLdiv
#define CLK_DIV_VAL ((Startup_PCLKdiv&&12)|(Startup_HCLKx2div&&9)|(Startup_HCLKdiv&&8)|(Startup_MPLLdiv&&4)|Startup_APLLdiv)
#if defined(CONFIG_SYNC_MODE)
#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
#define Startup_HCLK (Startup_MPLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
#if defined(FRIENDLYARM_BOOT_RAM256)
#define DMC1_MEM_CFG
((1&&30) | (2&&15) | (3&&3) | (2&&0))
#define DMC1_CHIP0_CFG
#define PHYS_SDRAM_1_SIZE 0x /* 256 MB */
#elif defined(FRIENDLYARM_BOOT_RAM128)
#define DMC1_MEM_CFG
((1&&30) | (2&&15) | (2&&3)| (2&&0))
#define DMC1_CHIP0_CFG
#define PHYS_SDRAM_1_SIZE 0x8000000 /* 128 MB */
#error RAM size must be defined
/*-----------------------------------------------------------------------
* Physical Memory Map
#define DMC1_MEM_CFG2
#define DMC_DDR_32_CFG
/* 32bit, DDR */
/* Memory Parameters */
/* DDR Parameters */
#define DDR_tREFRESH
#define DDR_tRAS
/* ns (min: 45ns)*/
#define DDR_tRC
/* ns (min: 67.5ns)*/
#define DDR_tRCD
/* ns (min: 22.5ns)*/
#define DDR_tRFC
/* ns (min: 80ns)*/
#define DDR_tRP
/* ns (min: 22.5ns)*/
#define DDR_tRRD
/* ns (min: 15ns)*/
#define DDR_tWR
/* ns (min: 15ns)*/
#define DDR_tXSR
/* ns (min: 120ns)*/
#define DDR_CASL
/* CAS Latency 3 */
* mDDR memory configuration
#define DMC_DDR_BA_EMRS
#define DMC_DDR_MEM_CASLAT 3
#define DMC_DDR_CAS_LATENCY (DDR_CASL&&1)
Set Cas Latency to 3
#define DMC_DDR_t_DQSS
// Min 0.75 ~ 1.25
#define DMC_DDR_t_MRD
//Min 2 tck
#define DMC_DDR_t_RAS
(((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1) //7, Min 45ns
#define DMC_DDR_t_RC
(((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1)
//10, Min 67.5ns
#define DMC_DDR_t_RCD
(((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1)
//4,5(TRM), Min 22.5ns
#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) && 3)
#define DMC_DDR_t_RFC
(((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1)
//11,18(TRM) Min 80ns
#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) && 5)
#define DMC_DDR_t_RP
(((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1)
//4, 5(TRM) Min 22.5ns
#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) && 3)
#define DMC_DDR_t_RRD
(((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1) //3, Min 15ns
#define DMC_DDR_t_WR
(((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1) //Min 15ns
#define DMC_DDR_t_WTR
#define DMC_DDR_t_XP
//1tck + tIS(1.5ns)
#define DMC_DDR_t_XSR
(((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1) //17, Min 120ns
#define DMC_DDR_t_ESR
DMC_DDR_t_XSR
#define DMC_DDR_REFRESH_PRD (((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000)
// TRM 2656
#define DMC_DDR_USER_CONFIG 1
// 2b01 : mDDR
#define CONFIG_NR_DRAM_BANKS 1
/* we have 2 bank of DRAM */
#define PHYS_SDRAM_1
MEMORY_BASE_ADDRESS /* SDRAM Bank #1 */
//#define PHYS_SDRAM_1_SIZE 0x /* 128 MB */
/* total memory required by uboot */
#define CFG_UBOOT_SIZE
/* base address */
#define CFG_PROG_BASE
MEMORY_BASE_ADDRESS
#define CFG_PHY_UBOOT_BASE MEMORY_BASE_ADDRESS
#endif /* __CONFIG_H */
#include &config.h&
//#include &version.h&
//#include &regs.h&
#ifndef CONFIG_ENABLE_MMU
#ifndef CFG_PHY_UBOOT_BASE
#define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE
*************************************************************************
* Jump vector table as in table 3.1 in [1]
*************************************************************************
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction:
.word undefined_instruction
_software_interrupt:
.word software_interrupt
_prefetch_abort:
.word prefetch_abort
_data_abort:
.word data_abort
_not_used:
.word not_used
.word 0x /* now 16*4=64 */
.global _end_vect
_end_vect:
.balignl 16,0xdeadbeef
*************************************************************************
* Startup Code (reset vector)
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*************************************************************************
_TEXT_BASE:
.word TEXT_BASE
* Below variable is very important because we use MMU in U-Boot.
* Without it, we cannot run code correctly before MMU is ON.
* by scsuh.
_TEXT_PHY_BASE:
.word CFG_PHY_UBOOT_BASE
.globl _armboot_start
_armboot_start:
.word _start
* These are defined in the board-specific linker script.
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
.word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
* the actual reset code
* set the cpu to SVC32 mode
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
*************************************************************************
* CPU_init_critical registers
* setup important registers
* setup memory timing
*************************************************************************
* we do sys-critical inits only at reboot,
* not when booting from ram!
cpu_init_crit:
* flush v4 I/D caches
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
* disable MMU stuff and caches
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x @ set bit 2 (A) Align
orr r0, r0, #0x @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
/* Peri port setup */
ldr r0, =0x
orr r0, r0, #0x13
mcr p15,0,r0,c15,c2,4
@ 256M(0xx7fffffff)
* Go setup Memory and board specific bits prior to relocation.
bl lowlevel_init /* go setup pll,mux,memory */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0xC00
str r1, [r0, #GPPDAT_OFFSET]
ldr r1, [r0, #GPFPUD_OFFSET]
bic r1, r1, #0xc0000000
orr r1, r1, #0x
str r1, [r0, #GPFPUD_OFFSET]
ldr r1, [r0, #GPFDAT_OFFSET]
orr r1, r1, #0x8000
str r1, [r0, #GPFDAT_OFFSET]
ldr r1, [r0, #GPFCON_OFFSET]
bic r1, r1, #0xc0000000
orr r1, r1, #0x
str r1, [r0, #GPFCON_OFFSET]
skip_hw_init:
/* Set up the stack
stack_setup:
ldr r0, _bss_start
/* upper 128 KiB: relocated uboot
add r0, r0, #CFG_MALLOC_LEN /* malloc area
add r0, r0, #CONFIG_STACKSIZE_SVC
mov sp, r0
clear_bss:
ldr r0, _bss_start
/* find start of bss segment
ldr r1, _bss_end
/* stop here
str r2, [r0]
/* clear loop...
add r0, r0, #4
cmp r0, r1
ble clbss_l
ldr pc, _start_armboot
_start_armboot:
.word start_armboot
*************************************************************************
* Interrupt handling
*************************************************************************
@ IRQ stack frame.
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR
#define S_PC
#define S_LR
#define S_SP
#define S_IP
#define S_FP
#define S_R10
#define S_R9
#define S_R8
#define S_R7
#define S_R6
#define S_R5
#define S_R4
#define S_R3
#define S_R2
#define S_R1
#define S_R0
#define MODE_SVC 0x13
#define I_BIT
* exception handlers
undefined_instruction:
b undefined_instruction
software_interrupt:
b software_interrupt
prefetch_abort:
b prefetch_abort
data_abort:
b data_abort
b not_used
#ifdef CONFIG_USE_IRQ
cpu_init.S
#include &config.h&
#include &s3c6410.h&
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
ldr r0, =ELFIN_MEM_SYS_CFG
@Memory sussystem address 0x7e00f120
mov r1, #0xd
@ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1
str r1, [r0]
ldr r0, =ELFIN_DMC1_BASE
@DMC1 base address 0x7e001000
ldr r1, =0x04
str r1, [r0, #INDEX_DMC_MEMC_CMD]
ldr r1, =DMC_DDR_REFRESH_PRD
str r1, [r0, #INDEX_DMC_REFRESH_PRD]
ldr r1, =DMC_DDR_CAS_LATENCY
str r1, [r0, #INDEX_DMC_CAS_LATENCY]
ldr r1, =DMC_DDR_t_DQSS
str r1, [r0, #INDEX_DMC_T_DQSS]
ldr r1, =DMC_DDR_t_MRD
str r1, [r0, #INDEX_DMC_T_MRD]
ldr r1, =DMC_DDR_t_RAS
str r1, [r0, #INDEX_DMC_T_RAS]
ldr r1, =DMC_DDR_t_RC
str r1, [r0, #INDEX_DMC_T_RC]
ldr r1, =DMC_DDR_t_RCD
ldr r2, =DMC_DDR_schedule_RCD
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RCD]
ldr r1, =DMC_DDR_t_RFC
ldr r2, =DMC_DDR_schedule_RFC
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RFC]
ldr r1, =DMC_DDR_t_RP
ldr r2, =DMC_DDR_schedule_RP
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RP]
ldr r1, =DMC_DDR_t_RRD
str r1, [r0, #INDEX_DMC_T_RRD]
ldr r1, =DMC_DDR_t_WR
str r1, [r0, #INDEX_DMC_T_WR]
ldr r1, =DMC_DDR_t_WTR
str r1, [r0, #INDEX_DMC_T_WTR]
ldr r1, =DMC_DDR_t_XP
str r1, [r0, #INDEX_DMC_T_XP]
ldr r1, =DMC_DDR_t_XSR
str r1, [r0, #INDEX_DMC_T_XSR]
ldr r1, =DMC_DDR_t_ESR
str r1, [r0, #INDEX_DMC_T_ESR]
ldr r1, =DMC1_MEM_CFG
str r1, [r0, #INDEX_DMC_MEMORY_CFG]
ldr r1, =DMC1_MEM_CFG2
str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
ldr r1, =DMC1_CHIP0_CFG
str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
ldr r1, =DMC_DDR_32_CFG
str r1, [r0, #INDEX_DMC_USER_CONFIG]
@DMC0 DDR Chip 0 configuration direct command reg
ldr r1, =DMC_NOP0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Precharge All
ldr r1, =DMC_PA0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Auto Refresh 2 time
ldr r1, =DMC_AR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
ldr r1, =DMC_mDDR_EMR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
ldr r1, =DMC_mDDR_MR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
#ifdef CONFIG_SMDK6410_X5A
ldr r1, =DMC1_CHIP1_CFG
str r1, [r0, #INDEX_DMC_CHIP_1_CFG]
@DMC0 DDR Chip 0 configuration direct command reg
ldr r1, =DMC_NOP1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Precharge All
ldr r1, =DMC_PA1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Auto Refresh 2 time
ldr r1, =DMC_AR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
ldr r1, =DMC_mDDR_EMR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
ldr r1, =DMC_mDDR_MR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Enable DMC1
mov r1, #0x0
str r1, [r0, #INDEX_DMC_MEMC_CMD]
check_dmc1_ready:
ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
bne check_dmc1_ready
mov pc, lr
/* Below code is for ARM926EJS and ARM1026EJS */
.globl cleanDCache
cleanDCache:
mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
bne cleanDCache
mov pc, lr
.globl cleanFlushDCache
cleanFlushDCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushDCache
mov pc, lr
.globl cleanFlushCache
cleanFlushCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushCache
mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
mov pc, lr
lowlevel_init.S
* Memory Setup stuff - taken from blob memsetup.S
* Copyright (C) 01 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
* Modified for the Samsung SMDK2410 by
* (C) Copyright 2002
* David Mueller, ELSOFT AG, &d.mueller@elsoft.ch&
* See file CREDITS for list of people who contributed to this
* project.
* This prog you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software F either version 2 of
* the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* alo if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#include &config.h&
#include &s3c6410.h&
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
lowlevel_init:
mov r12, lr
/* LED on only #8 */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x
str r1, [r0, #GPNCON_OFFSET]
ldr r1, =0x
str r1, [r0, #GPNPUD_OFFSET]
ldr r1, =0xf000
str r1, [r0, #GPNDAT_OFFSET]
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x1
str r1, [r0, #GPECON_OFFSET]
ldr r1, =0x0
str r1, [r0, #GPEDAT_OFFSET]
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x2A5AAAAA
str r1, [r0, #GPPCON_OFFSET]
ldr r1, =0x0
str r1, [r0, #GPPDAT_OFFSET]
ldr r1, =0x
str r1, [r0, #MEM1DRVCON_OFFSET]
/* Disable Watchdog */
ldr r0, =0x7e000000
@0x7e004000
orr r0, r0, #0x4000
mov r1, #0
str r1, [r0]
@ External interrupt pending clear
ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
ldr r1, [r0]
str r1, [r0]
ldr r0, =ELFIN_VIC0_BASE_ADDR
ldr r1, =ELFIN_VIC1_BASE_ADDR
@ Disable all interrupts (VIC0 and VIC1)
mvn r3, #0x0
str r3, [r0, #oINTMSK]
str r3, [r1, #oINTMSK]
@ Set all interrupts as IRQ
mov r3, #0x0
str r3, [r0, #oINTMOD]
str r3, [r1, #oINTMOD]
@ Pending Interrupt Clear
mov r3, #0x0
str r3, [r0, #oVECTADDR]
str r3, [r1, #oVECTADDR]
/* init system clock */
bl system_clock_init
/* for UART */
bl uart_asm_init
#if defined(CONFIG_NAND)
/* simple init for NAND */
bl nand_asm_init
ldr r0, =0xff000fff
bic r1, pc, r0
/* r0 &- current base addr of code */
ldr r2, _TEXT_BASE
/* r1 &- original base addr in ram */
bic r2, r2, r0
/* r0 &- current base addr of code */
/* compare r0, r1
/* r0 == r1 then skip sdram init
bl mem_ctrl_asm_init
r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
r1, r1, #0xfffffff7
wakeup_reset
ldr r0, =ELFIN_UART_BASE
ldr r1, =0x4b4b4b4b
str r1, [r0, #UTXH_OFFSET]
mov lr, r12
mov pc, lr
wakeup_reset:
/*Clear wakeup status register*/
ldr r0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
ldr r1, [r0]
str r1, [r0]
/*LED test*/
r0, =ELFIN_GPIO_BASE
r1, =0x3000
r1, [r0, #GPNDAT_OFFSET]
/*Load return address and jump to kernel*/
ldr r0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
ldr r1, [r0] /* r1 = physical address of s3c6400_cpu_resume function*/
mov pc, r1
/*Jump to kernel (sleep-s3c6400.S)*/
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
system_clock_init:
ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
#ifdef CONFIG_SYNC_MODE
ldr r1, [r0, #OTHERS_OFFSET]
mov r2, #0x40
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
ldr r2, =0x80
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
check_syncack:
ldr r1, [r0, #OTHERS_OFFSET]
ldr r2, =0xf00
and r1, r1, r2
cmp r1, #0xf00
bne check_syncack
#else /* ASYNC Mode */
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0xC0
orr r1, r1, #0x40
str r1, [r0, #OTHERS_OFFSET]
wait_for_async:
ldr r1, [r0, #OTHERS_OFFSET]
and r1, r1, #0xf00
cmp r1, #0x0
bne wait_for_async
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0x40
str r1, [r0, #OTHERS_OFFSET]
mov r1, #0xff00
orr r1, r1, #0xff
str r1, [r0, #APLL_LOCK_OFFSET]
str r1, [r0, #MPLL_LOCK_OFFSET]
str r1, [r0, #EPLL_LOCK_OFFSET]
/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */
/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
#if defined(CONFIG_CLKSRC_CLKUART)
r1, [r0, #CLK_DIV2_OFFSET]
bic r1, r1, #0x70000
orr r1, r1, #0x30000
str r1, [r0, #CLK_DIV2_OFFSET]
r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =CLK_DIV_VAL
orr r1, r1, r2
str r1, [r0, #CLK_DIV0_OFFSET]
ldr r1, =APLL_VAL
str r1, [r0, #APLL_CON_OFFSET]
ldr r1, =MPLL_VAL
str r1, [r0, #MPLL_CON_OFFSET]
ldr r1, =0x
/* FOUT of EPLL is 96MHz */
str r1, [r0, #EPLL_CON0_OFFSET]
ldr r1, =0x0
str r1, [r0, #EPLL_CON1_OFFSET]
ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */
#if defined(CONFIG_CLKSRC_CLKUART)
ldr r2, =0x2007
ldr r2, =0x7
orr r1, r1, r2
str r1, [r0, #CLK_SRC_OFFSET]
/* wait at least 200us to stablize all clock */
mov r1, #0x10000
1: subs r1, r1, #1
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0xc0000000 /* clock setting in MMU */
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_SYNC_MODE
/* Synchronization for VIC port */
ldr r1, [r0, #OTHERS_OFFSET]
orr r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
ldr r1, [r0, #OTHERS_OFFSET]
bic r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
mov pc, lr
* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
* void uart_asm_init(void)
uart_asm_init:
/* set GPIO to enable UART */
@ GPIO setting for UART
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x
r1, [r0, #GPACON_OFFSET]
ldr r1, =0x2222
r1, [r0, #GPBCON_OFFSET]
ldr r0, =ELFIN_UART_CONSOLE_BASE
@0x7F005000
mov r1, #0x0
str r1, [r0, #UFCON_OFFSET]
str r1, [r0, #UMCON_OFFSET]
mov r1, #0x3
str r1, [r0, #ULCON_OFFSET]
#if defined(CONFIG_CLKSRC_CLKUART)
ldr r1, =0xe45
/* UARTCLK SRC = 11 =& EXT_UCLK1*/
ldr r1, =0x245
/* UARTCLK SRC = x0 =& PCLK */
str r1, [r0, #UCON_OFFSET]
#if defined(CONFIG_UART_50)
ldr r1, =0x1A
#elif defined(CONFIG_UART_66)
ldr r1, =0x22
ldr r1, =0x1A
str r1, [r0, #UBRDIV_OFFSET]
#if defined(CONFIG_UART_50)
ldr r1, =0x3
#elif defined(CONFIG_UART_66)
ldr r1, =0x1FFF
ldr r1, =0x3
str r1, [r0, #UDIVSLOT_OFFSET]
ldr r1, =0x4f4f4f4f
str r1, [r0, #UTXH_OFFSET]
mov pc, lr
* Nand Interface Init for SMDK6400 */
nand_asm_init:
ldr r0, =ELFIN_NAND_BASE
ldr r1, [r0, #NFCONF_OFFSET]
orr r1, r1, #0x70
orr r1, r1, #0x7700
r1, [r0, #NFCONF_OFFSET]
ldr r1, [r0, #NFCONT_OFFSET]
orr r1, r1, #0x03
r1, [r0, #NFCONT_OFFSET]
mov pc, lr
#ifdef CONFIG_ENABLE_MMU
* MMU Table for SMDK6400
/* form a first-level section entry */
.macro FL_SECTION_ENTRY base,ap,d,c,b
.word (\base && 20) | (\ap && 10) | \
(\d && 5) | (1&&4) | (\c && 3) | (\b && 2) | (1&&1)
.section .mmudata, &a&
// the following alignment creates the mmu table at address 0x4000.
.globl mmu_table
mmu_table:
.set __base,0
// 1:1 mapping for debugging
.rept 0xA00
FL_SECTION_ENTRY __base,3,0,0,0
.set __base,__base+1
// access is not allowed.
.rept 0xC00 - 0xA00
// 128MB for SDRAM 0xC0000000 -& 0x
.set __base, 0x500
.rept 0xC80 - 0xC00
FL_SECTION_ENTRY __base,3,0,1,1
.set __base,__base+1
// access is not allowed.
.rept 0x1000 - 0xc80
start_armboot.c
#include &s3c6410.h&
#include &stdio.h&
//#define DDR_TEST
#define TEST_LED
#ifdef DDR_TEST
static void TestDDR();
#ifdef TEST_LED
static void test_led();
void start_armboot()
printf(&\r\n----------------------------\r\n&);
#ifdef DDR_TEST
TestDDR();
#ifdef TEST_LED
test_led();
printf(&123.\r\n&);
#ifdef DDR_TEST
static void TestDDR()
unsigned int ddr_base = 0x;
for(i = 0; i & 0x1000; i += 4)
*(unsigned int*)(ddr_base + i) =
if(*(unsigned int*)(ddr_base + i) != i)
*(unsigned int*)(ddr_base) = 0;
#ifdef TEST_LED
static void test_led()
int ledStatus = 0;
*(unsigned int*)(ELFIN_GPIO_BASE + GPKCON0_OFFSET) = 0x;
if(ledStatus)
*(unsigned int*)(ELFIN_GPIO_BASE + GPKDAT_OFFSET) = 0x00f0;
ledStatus = 0;
printf(&.&);
*(unsigned int*)(ELFIN_GPIO_BASE + GPKDAT_OFFSET) = 0x0000;
ledStatus = 1;
printf(&.&);
for(i = 0; i & 0x100000; i++);
gb6410.lds
OUTPUT_FORMAT(&elf32-littlearm&, &elf32-littlearm&, &elf32-littlearm&)
/*OUTPUT_FORMAT(&elf32-arm&, &elf32-arm&, &elf32-arm&)*/
OUTPUT_ARCH(arm)
ENTRY(_start)
. = ALIGN(4);
startup/start.o (.text)
startup/cpu_init.o (.text)
startup/lowlevel_init.o (.text)
startup/start_armboot.o (.text)
startup/putchar.o (.text)
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
PROGNAME = gb6410
TOP_DIR := $(CURDIR)
export TOP_DIR
CC := arm-linux-gcc
CXX := arm-linux-g++
AR := arm-linux-ar
LD := arm-linux-ld
OBJCOPY := arm-linux-objcopy
#######################################################################################################
INC_DIR_OPT :=
-I$(TOP_DIR)/inc
CPPFLAGS := -g -Wall $(INC_DIR_OPT) -DTEXT_BASE=0x
export CC CXX AR CPPFLAGS
########################################################################
SUBDIRS := $(TOP_DIR)/startup
#LIBS := $(TOP_DIR)/startup/libstartup.a
.PHONY: all $(SUBDIRS)
all: $(SUBDIRS)
$(LD) $(LDFLAGS) -o $(TOP_DIR)/$(PROGNAME) $(LIBS) -T gb6410.lds -Ttext 0x -Map gb6410.map
$(OBJCOPY) ${OBJCFLAGS} -O binary $(PROGNAME) $(PROGNAME).bin
@echo Success To Build Project.
$(SUBDIRS):
$(MAKE) -C $@ all
########################################################################
.PHONY:clean distclean cleanall
@for d in $(SUBDIRS); do \
$(MAKE) -C $$ \
distclean cleanall:
@for d in $(SUBDIRS); do \
$(MAKE) -C $$ \
$(RM) $(PROGNAME)
运行程序，在终端可以看到打印字符，板子上LED闪烁。
参考知识库
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