本篇文章主要介绍外设（PL）产生的中断请求，在PS端进行处理。&在PL端通过按键产生中断，PS接受到之后点亮相应的LED.
本文所使用的开发板是zedboardPC 开发环境版本：Vivado 2015.4 Xilinx SDK 2015.4
搭建硬件工程
建好工程后，添加ZYNQ IP
双击 ZYNQ,打开Re-customize IP对话框，使能IRQ_P2P
点击Run Connection Automation,按照如图所示配置，点击OK
添加一个GPIO IP,按照如图所示配置，使能中断。点击Run Connection Automation
再添加一个GPIO IP，按照如图所示配置,点击OK
把axi_gpio_0的ip2intc_irpt和ZYNQ PS的 IRQ_F2P[0:0]连在一起
搭建好的硬件系统连接，如图所示
生成顶层文件，点击Generate BitStream
新建一个Hello World工程，把以下代码添加进去
1 #include &stdio.h&
2 #include "platform.h"
3 #include "xparameters.h"
4 #include "xscugic.h"
5 #include "xil_exception.h"
6 #include "xgpio.h"
8 //parameter definitions
9 #define INTC_DEVICE_ID
XPAR_PS7_SCUGIC_0_DEVICE_ID
//DEVICE_ID用来初始化函数，索引数组元素
10 #define LED_DEVICE_ID
XPAR_AXI_GPIO_1_DEVICE_ID
11 #define BTNS_DEVICE_ID
XPAR_AXI_GPIO_0_DEVICE_ID
12 #define INTC_GPIO_INTERRUPT_ID
XPAR_FABRIC_AXI_GPIO_0_IP2INTC_IRPT_INTR
13 #define BTN_INT
XGPIO_IR_CH1_MASK
14 #define DELAY
16 XGpio LED;
17 XGpio BTNI
18 XScuGic
19 static int btn_
21 //Function protype
22 static void BTN_Intr_Handler(void *baseaddr_p);
23 static int InterruptSystemSetup(XScuGic *XScuGicInstancePtr);
24 static int IntcInitFunction(u16 DeviceId,XGpio *GpioInstancePtr);
26 void BTN_Intr_Handler(void *InstancePtr)
unsigned char led_val=0;
//Ignore additional button presses
if((XGpio_InterruptGetStatus(&BTNInst) & BTN_INT) != BTN_INT)
//Disable GPIO interrupts
XGpio_InterruptDisable(&BTNInst,BTN_INT);
btn_value = XGpio_DiscreteRead(&BTNInst,1);
switch(btn_value)
case 1: led_val = 0x01;break;
//led[7:0]=0x01
led_val = 0x02;break;
led_val = 0x03;break; //亮1和2
led_val = 0x04;break;
led_val = 0x05;break; //亮0和2
default:break;
XGpio_DiscreteWrite(&LED,1,led_val);
//Acknowledge GPIO interrupts
(void)XGpio_InterruptClear(&BTNInst,BTN_INT);
//Enable GPIO interrupts
XGpio_InterruptEnable(&BTNInst,BTN_INT);
54 int main(void)
//按键初始化
status = XGpio_Initialize(&BTNInst,BTNS_DEVICE_ID);
if(status != XST_SUCCESS) return XST_FAILURE;
//初始化LED
status = XGpio_Initialize(&LED,LED_DEVICE_ID);
if(status != XST_SUCCESS) return XST_FAILURE;
//设置按键IO的方向为输入
XGpio_SetDataDirection(&BTNInst,1,0xff);
//设置LED IO 的方向为输出
XGpio_SetDataDirection(&LED,1,0X00);
//初始化中断控制器
status = IntcInitFunction(INTC_DEVICE_ID,&BTNInst);
if(status != XST_SUCCESS) return XST_FAILURE;
while(1){}
80 int IntcInitFunction(u16 DeviceId,XGpio *GpioInstancePtr)
XScuGic_Config *IntcC
//Interrupt controller initialization
IntcConfig = XScuGic_LookupConfig(DeviceId);
status = XScuGic_CfgInitialize(&INTCInst,IntcConfig,IntcConfig-&CpuBaseAddress);
if(status != XST_SUCCESS) return XST_FAILURE;
//Call interrupt setup function
status = InterruptSystemSetup(&INTCInst);
if(status != XST_SUCCESS) return XST_FAILURE;
//Register GPIO interrupt handler
status = XScuGic_Connect(&INTCInst,INTC_GPIO_INTERRUPT_ID,(Xil_ExceptionHandler)BTN_Intr_Handler,(void *)GpioInstancePtr);
if(status != XST_SUCCESS) return XST_FAILURE;
//Enable GPIO interrupts
XGpio_InterruptEnable(GpioInstancePtr,1);
XGpio_InterruptGlobalEnable(GpioInstancePtr);
//Enable GPIO interrupts in the controller
XScuGic_Enable(&INTCInst,INTC_GPIO_INTERRUPT_ID);
return XST_SUCCESS;
108 int InterruptSystemSetup(XScuGic *XScuGicInstancePtr)
//Register GIC interrupt handler
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler)XScuGic_InterruptHandler,XScuGicInstancePtr);
Xil_ExceptionEnable();
return XST_SUCCESS;
下载好之后，按键按下可以看到相应的LED被点亮
阅读(...) 评论()->【Xilinx技术小组】
作者：Steve Leibson, 赛灵思战略营销与业务规划总监
现在我们的连载系列博客已经谈了如下话题：
o 用Vivado设计套件创建基于Zynq的系统
o 配置和启动
o 如何使用XADC
o 如何使用MIO和EMIO
o Zynq SoC的中断结构
o Zynq专用定时器和看门狗
o Zynq SoC三重定时器计数器
上述所有功能主要集中在Zynq SoC的处理系统（PS）。不过，从设计角度看，Zynq SoC真正让人兴奋的是用Zynq的可编程逻辑（PL）来开发应用，以及使用PL将处理任务从PS部分卸装到PL部分，这样既可加速任务完成，同时还可以收回处理器带宽用于其他任务。此外，在典型的SoC芯片应用中，PS部分还可以控制在PL部分执行的操作。
利用Zynq SoC的PL部分可以提升系统性能、降低功耗，并可以为实时事件提供可预测的延时，这对于嵌入式系统设计者来说都是天大的好事。
Zynq的 PS 和PL部分通过如下接口连接
o 两个32位AXI主端口（PS Master）
o 两个32位AXI从端口（PL Master）
o 四个32、/64位高性能端口（PL Master）
o 一个64位加速器一致性端口（ACP）(PL Master)
o 四个来自PS和PL的时钟
o PS到PL的中断
o PL到PS的中断
o DMA外设请求接口
这个方框图展示了这些不同的接口
ARM的AXI是丛发导向的协议，用于高带宽同时可提供低延迟。每个AXI端口包含独立的读写通道。有一种AXI协议用到很多接口，叫AXI4-精简版，它是一个简单的协议，可用于寄存器控制/状态接口。例如，Zynq XADC使用AXI4-精简版接口连接Zynq 的PS部分。
有关AXI更多详情请点击这里
在设备中的PS对接到PL侧时，Zynq SoC支持三种不同的AXI传输类型
o AXI4 丛发传输
o AXI4-Lite 用于简单控制接口
o AXI4流用于单向数据传输
每个接口的理论带宽定义如下
你必须使用Zynq SoC的DMA控制器来实现上表中的最高速度，另一项额外收益是当PS为master时，DMA控制器降低了Zynq SoC上的ARM Cortex-A9 MPCore处理器上的负荷，如果不使用DMA控制器，PS到PL的最大传输速率是是25Mbps。
总而言之，在PS和PL之间有14.4Gbps(115.2Gbps0的惊人理论带宽！在接下来的几个博客中，我们会更详细地介绍我们是如何创建和使用器件PL部分的外设以提高系统性能。作为工程师，我们有责任选择最优的接口、使用最具成本效益的方法来达到理想的系统性能。
这里也可以看看亚当泰勒玩转MicroZed系列其他文章
原文链接：深入浅出FPGA-17-xilinx_zynq7000_EPP上一个简单实验(PS+PL)
前面两个实验，PL是传统的FPGA开发，PS是传统的嵌入式开发。
zynq7000EPP是xilinx比较高端的FPGA开发板，XC7Z020内部集成了两个cortexa9的硬核，外部有1G的DDR3，所以单纯做FPGA太浪费了。但是单纯用PS资源，就没必要用FPGA了，所以只有将两者结合使用才能体现其价值所在。
即，PS+PL。添加自己的一个IP到AXI总线上，然后通过SDK编码控制它的寄存器，这就是本小节的实验内容。
17.1 实验目的
1》& 熟悉zynq7000 EPP资源和design suite
2》& PL编码，PS编码，实现一个简单逻辑。
17.2&实验环境
Board ：ZYNQ7000 EPP
Device：XC7Z020CLG484ACX1221
Design suite：14.1 （PlanAhead+XPS+SDK）
17.3&&&实验准备
a)&&&&&&&&会planAhead创建工程：ps_pl。
b)&&&&&&&&简单了解和使用XPS和SDK
17.4 &实验内容
a)&&&&&&&&添加自己一个IP:rill_ip，挂到AXI上，此IP有一个output连到外部一个LED上。
b)&&&&&&&&在SDK编写C代码控制这个IP的寄存器来控制此设备，进而控制LED的闪烁。
17.5&实验步骤
a)&&&&&&&&打开planAhead，创建embedded新工程，添加PS7。
b)&&&&&&&&打开XPS-&hardware，添加自己的ip：rill_ip。
c)&&&&&&&&AXI4-lite.
d)&&&&&&&&一个32位寄存器。
e)&&&&&&&&生成driver。
f)&&&&&&&&&修改此IP的文件：MPD文件，rill_ip.vhd，user_logic.vhd。三个文件。
File:mpd,1个地方需要修改，如图：这3个文件的路径很深，不好找，截图上面有路径，方便很多。
可以根据截图找到对应位置，然后添加相应代码。
也可以参考附录代码。
File:rill_ip.vhd: 2个地方需要修改。
File:user_logic.vhd: 3个地方需要修改。
g)&&&&&&&&将此ip添加到XPS工程。
h)&&&&&&&&自动映射。注意port名称，ucf文件里要用。
i)&&&&&&&&&&添加UCF文件，内容：ps_pl.ucf。
j)&&&&&&&&&&Create TOP HDL，然后生成bitstream。
k)&&&&&&&&&导出hardware，launch SDK。
l)&&&&&&&&&&在SDK里创建helloword工程。
m)&&&&&&SDK编码，内容：helloworld.c。读写寄存器。
n)&&&&&&&&Program FPGA
o)&&&&&&&&Run AS,configure
p)&&&&&&&&Run
17.6 &实验结果
看板子，DS18这个led会由亮变灭：串口也有打印。
文件1：rill_ip_v2_1_0.mpd：
###################################################################
: Microprocessor Peripheral Description
: Automatically generated by PsfUtility
###################################################################
BEGIN rill_ip
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:USER
OPTION DESC = RILL_IP
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 0, DT = INTEGER
PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 1, DT = INTEGER
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
PORT led = &&,DIR = O
PORT S_AXI_ACLK = &&, DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
文件2：rill_ip.vhd
------------------------------------------------------------------------------
-- rill_ip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
-- ***************************************************************************
-- ** Copyright (c)
Xilinx, Inc.
All rights reserved.
-- ** Xilinx, Inc.
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION &AS IS&
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- ** SOLUTIONS FOR XILINX DEVICES.
BY PROVIDING THIS DESIGN, CODE,
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- ** FOR YOUR IMPLEMENTATION.
XILINX EXPRESSLY DISCLAIMS ANY
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- ** FOR A PARTICULAR PURPOSE.
-- ***************************************************************************
------------------------------------------------------------------------------
-- Filename:
rill_ip.vhd
-- Version:
-- Description:
Top level design, instantiates library components and user logic.
Mon Nov 05 13:53:37 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard:
------------------------------------------------------------------------------
-- Naming Conventions:
active low signals:
clock signals:
&clk&, &clk_div#&, &clk_#x&
reset signals:
&rst&, &rst_n&
user defined types:
state machine next state:
state machine current state:
combinatorial signals:
pipelined or register delay signals:
counter signals:
clock enable signals:
internal version of output port:
device pins:
&- Names begin with Uppercase&
processes:
&*_PROCESS&
component instantiations:
&&ENTITY_&I_&#|FUNC&&
------------------------------------------------------------------------------
use ieee.std_logic_1164.
use ieee.std_logic_arith.
use ieee.std_logic_unsigned.
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.
use proc_common_v3_00_a.ipif_pkg.
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_
library rill_ip_v1_00_a;
use rill_ip_v1_00_a.user_
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
C_S_AXI_DATA_WIDTH
-- AXI4LITE slave: Data width
C_S_AXI_ADDR_WIDTH
-- AXI4LITE slave: Address Width
C_S_AXI_MIN_SIZE
-- AXI4LITE slave: Min Size
C_USE_WSTRB
-- AXI4LITE slave: Write Strobe
C_DPHASE_TIMEOUT
-- AXI4LITE slave: Data Phase Timeout
C_BASEADDR
-- AXI4LITE slave: base address
C_HIGHADDR
-- AXI4LITE slave: high address
-- FPGA Family
-- Number of software accessible registers
-- Number of address-ranges
C_SLV_AWIDTH
-- Slave interface address bus width
C_SLV_DWIDTH
-- Slave interface data bus width
-- Definition of Ports:
S_AXI_ACLK
-- AXI4LITE slave: Clock
S_AXI_ARESETN
-- AXI4LITE slave: Reset
S_AXI_AWADDR
-- AXI4LITE slave: Write address
S_AXI_AWVALID
-- AXI4LITE slave: Write address valid
S_AXI_WDATA
-- AXI4LITE slave: Write data
S_AXI_WSTRB
-- AXI4LITE slave: Write strobe
S_AXI_WVALID
-- AXI4LITE slave: Write data valid
S_AXI_BREADY
-- AXI4LITE slave: Response ready
S_AXI_ARADDR
-- AXI4LITE slave: Read address
S_AXI_ARVALID
-- AXI4LITE slave: Read address valid
S_AXI_RREADY
-- AXI4LITE slave: Read data ready
S_AXI_ARREADY
-- AXI4LITE slave: read addres ready
S_AXI_RDATA
-- AXI4LITE slave: Read data
S_AXI_RRESP
-- AXI4LITE slave: Read data response
S_AXI_RVALID
-- AXI4LITE slave: Read data valid
S_AXI_WREADY
-- AXI4LITE slave: Write data ready
S_AXI_BRESP
-- AXI4LITE slave: Response
S_AXI_BVALID
-- AXI4LITE slave: Resonse valid
S_AXI_AWREADY
-- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity rill_ip is
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH
C_S_AXI_ADDR_WIDTH
C_S_AXI_MIN_SIZE
: std_logic_vector
:= X&000001FF&;
C_USE_WSTRB
C_DPHASE_TIMEOUT
C_BASEADDR
: std_logic_vector
:= X&FFFFFFFF&;
C_HIGHADDR
: std_logic_vector
:= &virtex6&;
C_SLV_AWIDTH
C_SLV_DWIDTH
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
led : OUT std_
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK
S_AXI_ARESETN
S_AXI_AWADDR
std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID
S_AXI_WDATA
std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB
std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID
S_AXI_BREADY
S_AXI_ARADDR
std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID
S_AXI_RREADY
S_AXI_ARREADY
: out std_
S_AXI_RDATA
: out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP
: out std_logic_vector(1 downto 0);
S_AXI_RVALID
: out std_
S_AXI_WREADY
: out std_
S_AXI_BRESP
: out std_logic_vector(1 downto 0);
S_AXI_BVALID
: out std_
S_AXI_AWREADY
: out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
attribute MAX_FANOUT :
attribute SIGIS :
attribute MAX_FANOUT of S_AXI_ACLK
: signal is &10000&;
attribute MAX_FANOUT of S_AXI_ARESETN
: signal is &10000&;
attribute SIGIS of S_AXI_ACLK
: signal is &Clk&;
attribute SIGIS of S_AXI_ARESETN
: signal is &Rst&;
end entity rill_
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of rill_ip is
constant USER_SLV_DWIDTH
:= C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH
:= C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD
: std_logic_vector(0 to 31) := (others =& '0');
constant USER_SLV_BASEADDR
: std_logic_vector
:= C_BASEADDR;
constant USER_SLV_HIGHADDR
: std_logic_vector
:= C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY
: SLV64_ARRAY_TYPE
ZERO_ADDR_PAD & USER_SLV_BASEADDR,
-- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR
-- user logic slave space high address
constant USER_SLV_NUM_REG
constant USER_NUM_REG
:= USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE
:= USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY
: INTEGER_ARRAY_TYPE
=& (USER_SLV_NUM_REG)
-- number of ce for user logic slave space
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX
constant USER_SLV_CE_INDEX
:= calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX
:= USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk
signal ipif_Bus2IP_Resetn
signal ipif_Bus2IP_Addr
: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW
signal ipif_Bus2IP_BE
: std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS
: std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE
: std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE
: std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data
: std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck
signal ipif_IP2Bus_RdAck
signal ipif_IP2Bus_Error
signal ipif_IP2Bus_Data
: std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE
: std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE
: std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data
: std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck
signal user_IP2Bus_WrAck
signal user_IP2Bus_Error
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
C_S_AXI_DATA_WIDTH
=& IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH
=& C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE
=& C_S_AXI_MIN_SIZE,
C_USE_WSTRB
=& C_USE_WSTRB,
C_DPHASE_TIMEOUT
=& C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY
=& IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY
=& IPIF_ARD_NUM_CE_ARRAY,
=& C_FAMILY
S_AXI_ACLK
=& S_AXI_ACLK,
S_AXI_ARESETN
=& S_AXI_ARESETN,
S_AXI_AWADDR
=& S_AXI_AWADDR,
S_AXI_AWVALID
=& S_AXI_AWVALID,
S_AXI_WDATA
=& S_AXI_WDATA,
S_AXI_WSTRB
=& S_AXI_WSTRB,
S_AXI_WVALID
=& S_AXI_WVALID,
S_AXI_BREADY
=& S_AXI_BREADY,
S_AXI_ARADDR
=& S_AXI_ARADDR,
S_AXI_ARVALID
=& S_AXI_ARVALID,
S_AXI_RREADY
=& S_AXI_RREADY,
S_AXI_ARREADY
=& S_AXI_ARREADY,
S_AXI_RDATA
=& S_AXI_RDATA,
S_AXI_RRESP
=& S_AXI_RRESP,
S_AXI_RVALID
=& S_AXI_RVALID,
S_AXI_WREADY
=& S_AXI_WREADY,
S_AXI_BRESP
=& S_AXI_BRESP,
S_AXI_BVALID
=& S_AXI_BVALID,
S_AXI_AWREADY
=& S_AXI_AWREADY,
Bus2IP_Clk
=& ipif_Bus2IP_Clk,
Bus2IP_Resetn
=& ipif_Bus2IP_Resetn,
Bus2IP_Addr
=& ipif_Bus2IP_Addr,
Bus2IP_RNW
=& ipif_Bus2IP_RNW,
=& ipif_Bus2IP_BE,
=& ipif_Bus2IP_CS,
Bus2IP_RdCE
=& ipif_Bus2IP_RdCE,
Bus2IP_WrCE
=& ipif_Bus2IP_WrCE,
Bus2IP_Data
=& ipif_Bus2IP_Data,
IP2Bus_WrAck
=& ipif_IP2Bus_WrAck,
IP2Bus_RdAck
=& ipif_IP2Bus_RdAck,
IP2Bus_Error
=& ipif_IP2Bus_Error,
IP2Bus_Data
=& ipif_IP2Bus_Data
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity rill_ip_v1_00_a.user_logic
generic map
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
=& USER_NUM_REG,
C_SLV_DWIDTH
=& USER_SLV_DWIDTH
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
led =& led,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk
=& ipif_Bus2IP_Clk,
Bus2IP_Resetn
=& ipif_Bus2IP_Resetn,
Bus2IP_Data
=& ipif_Bus2IP_Data,
=& ipif_Bus2IP_BE,
Bus2IP_RdCE
=& user_Bus2IP_RdCE,
Bus2IP_WrCE
=& user_Bus2IP_WrCE,
IP2Bus_Data
=& user_IP2Bus_Data,
IP2Bus_RdAck
=& user_IP2Bus_RdAck,
IP2Bus_WrAck
=& user_IP2Bus_WrAck,
IP2Bus_Error
=& user_IP2Bus_Error
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data &= user_IP2Bus_D
ipif_IP2Bus_WrAck &= user_IP2Bus_WrA
ipif_IP2Bus_RdAck &= user_IP2Bus_RdA
ipif_IP2Bus_Error &= user_IP2Bus_E
user_Bus2IP_RdCE &= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE &= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
文件3：user_logic.vhd
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- ***************************************************************************
-- ** Copyright (c)
Xilinx, Inc.
All rights reserved.
-- ** Xilinx, Inc.
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION &AS IS&
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- ** SOLUTIONS FOR XILINX DEVICES.
BY PROVIDING THIS DESIGN, CODE,
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- ** FOR YOUR IMPLEMENTATION.
XILINX EXPRESSLY DISCLAIMS ANY
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- ** FOR A PARTICULAR PURPOSE.
-- ***************************************************************************
------------------------------------------------------------------------------
-- Filename:
user_logic.vhd
-- Version:
-- Description:
User logic.
Mon Nov 05 13:53:37 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard:
------------------------------------------------------------------------------
-- Naming Conventions:
active low signals:
clock signals:
&clk&, &clk_div#&, &clk_#x&
reset signals:
&rst&, &rst_n&
user defined types:
state machine next state:
state machine current state:
combinatorial signals:
pipelined or register delay signals:
counter signals:
clock enable signals:
internal version of output port:
device pins:
&- Names begin with Uppercase&
processes:
&*_PROCESS&
component instantiations:
&&ENTITY_&I_&#|FUNC&&
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
use ieee.std_logic_1164.
use ieee.std_logic_arith.
use ieee.std_logic_unsigned.
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- Number of software accessible registers
C_SLV_DWIDTH
-- Slave interface data bus width
-- Definition of Ports:
Bus2IP_Clk
-- Bus to IP clock
Bus2IP_Resetn
-- Bus to IP reset
Bus2IP_Data
-- Bus to IP data bus
-- Bus to IP byte enables
Bus2IP_RdCE
-- Bus to IP read chip enable
Bus2IP_WrCE
-- Bus to IP write chip enable
IP2Bus_Data
-- IP to Bus data bus
IP2Bus_RdAck
-- IP to Bus read transfer acknowledgement
IP2Bus_WrAck
-- IP to Bus write transfer acknowledgement
IP2Bus_Error
-- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
led : out std_
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk
Bus2IP_Resetn
Bus2IP_Data
std_logic_vector(C_SLV_DWIDTH-1 downto 0);
std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE
std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE
std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data
: out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck
: out std_
IP2Bus_WrAck
: out std_
IP2Bus_Error
: out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
attribute MAX_FANOUT :
attribute SIGIS :
attribute SIGIS of Bus2IP_Clk
: signal is &CLK&;
attribute SIGIS of Bus2IP_Resetn : signal is &RST&;
end entity user_
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
signal led_i : std_
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0
: std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel
: std_logic_vector(0 to 0);
signal slv_reg_read_sel
: std_logic_vector(0 to 0);
signal slv_ip2bus_data
: std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack
signal slv_write_ack
--USER logic implementation added here
led_PROC : process (Bus2IP_Clk) is
if Bus2IP_WrCE(0) = '1' then
led_i &= '1';
led_i &= '0';
end process led_PROC;
led &= led_i;
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
Bus2IP_WrCE/Bus2IP_RdCE
Memory Mapped Register
C_BASEADDR + 0x0
C_BASEADDR + 0x4
C_BASEADDR + 0x8
C_BASEADDR + 0xC
------------------------------------------
slv_reg_write_sel &= Bus2IP_WrCE(0 downto 0);
slv_reg_read_sel
&= Bus2IP_RdCE(0 downto 0);
slv_write_ack
&= Bus2IP_WrCE(0);
slv_read_ack
&= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 &= (others =& '0');
case slv_reg_write_sel is
when &1& =&
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) &= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
when others =&
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
case slv_reg_read_sel is
when &1& =& slv_ip2bus_data &= slv_reg0;
when others =& slv_ip2bus_data &= (others =& '0');
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data
&= slv_ip2bus_data when slv_read_ack = '1' else
(others =& '0');
IP2Bus_WrAck &= slv_write_
IP2Bus_RdAck &= slv_read_
IP2Bus_Error &= '0';
文件4：UCF文件
NET rill_ip_0_led_pin IOSTANDARD=LVCMOS25 | LOC=V7;
文件5：SDK编码
* Copyright (c) 2009 Xilinx, Inc.
All rights reserved.
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION &AS IS& AS A
* COURTESY TO YOU.
BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE
IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
* helloworld.c: simple test application
#include &stdio.h&
#include &platform.h&
#include &../../hello_world_bsp_0/ps7_cortexa9_0/include/xgpiops_hw.h&
#include &../../hello_world_bsp_0/ps7_cortexa9_0/include/xparameters.h&
#define LED_BASE_ADDR XPAR_RILL_IP_0_BASEADDR
void my_process(void);
int main()
init_platform();
my_process();
cleanup_platform();
void my_process(void)
int ret = 0;
printf(&my_process start...&);
ret = XGpioPs_ReadReg(LED_BASE_ADDR, 0);
printf(&read0 :%d\n\n&,ret);
XGpioPs_WriteReg(LED_BASE_ADDR, 0, 0);
ret = XGpioPs_ReadReg(LED_BASE_ADDR, 0);
printf(&read1 :%d\n\n&,ret);
XGpioPs_WriteReg(LED_BASE_ADDR, 0, 1);
ret = XGpioPs_ReadReg(LED_BASE_ADDR, 0);
printf(&read2 :%d\n\n&,ret);
/************ EOF *************/
这三个实验包含了高端FPGA的主要的三种开发方式。也是典型的使用方式。这三个小实验搞明白了的话，就算入门了吧。
再进一步的话，只不过是逻辑复杂些，代码量多一些。这就需要其他方面的知识和技能了。
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