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TOSHIBA Satellite L310 Quanta TE1M_图文
BOM P/N 31TE1MBMBMBMB0140
Description
TE1M MB(PM45/RB/MS)WO CPU TE1M MB(PM45/MAIN/RB/HDMI/CIR)WO CPU TE1M MB(GM45/EXP/NO CIR/MS)WO CPU TE1M MB(GM45/GS/EXP/MS)WO CPU TE1M MB(GM45/GS/EXP/LC)WO CPU TE1M MB(GM45/HDMI/EXP/MS)WO CPU TE1M MB(GM45/HDMI/GS/CIR/MS)WO CPU TE1M MB ASY(GL40/PC/GS/FE/HD/KI,MS)WOCPU TE1M MB ASY(GM45/PC/GS/FE/HD/KI,MS)WOCPU TE1M MB(PM45/HDMI/NO CIR/MS)WO CPU
TE1M Block Diagram
478P uFCPGA
31TE1MBMB01N0 31TE1MB01M0 31TE1MB01P0 31TE1MB01Q0 31TE1MB01S0
EXT_LVDS EXT_HDMI SWITCH CIRCUIT
FSB(667/800/1066MHZ)
DDR SYSTEM MEMORY FSB
LCD/CCD Con.
P5,7,8,9,10,11 DMI
Graphics Interfaces
DDRII-SODIMM1 DDRII-SODIMM2
Dual Channel DDR II 667/800 MHZ
PCI-E x16 PCIE INT_CRT INT_LVDS I2C
PI3VDP411LST HDMI level shift
LED/CCD Con.
PCB STACK UP
LAYER 1 : TOP LAYER 2 : GND1
SATA - HDD
R5F211A4SP CEC P21
SATA - ODD
DMI(x2/x4) SATA 0 SATA 1
SATA DMI PCI-E PCI-Express PCIE-2 PCIE-1 USB-9 P27
LAYER 3 : IN1 LAYER 4 : VCC LAYER 5 : IN2 LAYER 6 : IN3 LAYER 7 : GND2 LAYER 8 : BOT
BOM Option Table Reference
NEW CARD Con. MINI CARD-3 U 9H_HD-DVD
ICS9LPR365
CLOCK GENERATOR
PI2EQX3201B Re-driver P27
PCIE-3 USB-8 MINI CARD-2 U 5.6H_TV/ROBSON D 7.5H_HD-DVD P25
Finger Printer
USB 2.0 (Port0~9)
Description
INT VGA EXT VGA
Bluetooth Con.
USB-2 RTC USB-4
Intel I/O Controller Hub 9 (ICH9M)
P12, 13, 14, 15
MINI CARD-4 (FTB) D ROBSON
PCIE-5 USB-0 Port-C (FM) P26 PCIE-6 USB-5
LAN/ USB/ FM Con.
POWER SYSTEM ISL88731 ISL6237 ISL6266A RT8202 TPS51116 APL LED POWER DRIVER ISL97636
P31 P32 P33 P34 P35 P36 P36 P19
Felica Con.
MINI CARD-1 U&D 5.6H_WLAN
W25X16VSS1G SPI FLASH P13 MDC Con.
PCMCIA Controller
PCMCIA SOCKET
+1.5V +1.05V
Cardreader/1394 Controller
Cardreader Con. P24 5 IN 1 1394 Con.
LPC INT_ MIC
+1.8VSUS +1.8V
+1.5V_S5 +3VPCU +3V_S5 +3VSUS +3V +5VPCU +5V_S5 +5V +SMDDR_VTERM +SMDDR_VREF
CX20561-12Z AUDIO CODEC
P29 Port-B Port-A
WPC8763LDG EC
P29 Port-C (FM)
VR MIC JACK
LIS3L02AQ3 G-Sensor
MMB Board Con. P26
Touch Pad Board Con. P26
Power Board Con. P26
W25X16VSS1G SPI FLASH
HALL SENSOR
Low Cost Board Con. P26
LED Board Con. P26
Size Date: Document Number
Quanta Computer Inc.
PROJECT : TE1M
Block Diagram
Monday, May 26, 2008 Sheet
Rev E3D 1 of 40
Clock Generator
+3V L518 PBY1Y-N_6 C700 0.1u/10V_4 C204 *10u/10V_8 C704 C695 10u/10V_8 C706 10u/10V_8 0.1u/10V_4 C205 10u/10V_8 C685 0.1u/10V_4 C206 0.1u/10V_4 C207 0.1u/10V_4 C677 0.1u/10V_4 C211
+1.05V_VDD
BOM Option Table
PBY1Y-N_6 L17
Description
INT VGA EXT VGA
C208 0.1u/10V_4
0.1u/10V_4
C694 C676 +3V C643 PM_STPPCI# PM_STPCPU# NEW_CLKREQ#_R R219 R218 2.2K_4 C699 2.2K_4
0.1u/10V_4 0.1u/10V_4 VDD_CK_VDD_PCI VDD_CK_VDD_48 VDD_CK_VDD_PCI VDD_CK_VDD_REF VDD_CK_VDD_PCI VDD_CK_VDD_CPU +1.05V_VDD
2 9 16 61 39 55 12 20 26 45 36 49
VDD_PCI VDD_48 VDD_PLL3 VDD_REF VDD_SRC VDD_CPU
IO_VOUT SCLK SDA
48 64 63 38 37 54 53 51 50 47 46 35 34 33 32 30 31 44 43 41 40 27 28 24 25 21 22 17 18 13 14 56
CGCLK_SMB CGDAT_SMB PM_STPPCI# PM_STPCPU# CLK_CPU_BCLK_R CLK_CPU_BCLK#_R CLK_MCH_BCLK_R CLK_MCH_BCLK#_R CLK_PCIE_MINI2&4_R CLK_PCIE_MINI2&4#_R CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R CLK_MCH_OE#_R NEW_CLKREQ#_R CLK_PCIE_NEW_R CLK_PCIE_NEW_R# CLK_PCIE_MINI3_R CLK_PCIE_MINI3#_R CLK_PCIE_MINI_R CLK_PCIE_MINI#_R CLK_PCIE_LAN_R CLK_PCIE_LAN#_R CLK_PCIE_ICH_R CLK_PCIE_ICH#_R CLK_PCIE_SATA_R CLK_PCIE_SATA#_R DREFSSCLK_R DREFSSCLK#_R DREFCLK_R DREFCLK#_R RP53 RP42 R217 R216 RP43 RP47 RP45 RP52 RP50 PM_STPPCI# 14 PM_STPCPU# 14
0.1u/10V_4
SRC5/PCI_STOP# SRC5#/CPU_STOP# CPU0 CPU0# CPU1 CPU1# SRC8/ITP SRC8#/ITP#
To SB To CPU To NB
0.1u/10V_4
VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO
2 0X2 4 2 0X2 4
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5
25 PCLK_DEBUG 23 PCLK_PCM 24 PCLK_OZ129 C226 27p/50V_4 CG_XIN Y3 14.318MHZ C239 27p/50V_4 28 13 PCLK_591 PCLK_ICH PCLK_591 PCLK_ICH PCLK_OZ129 PCLK_DEBUG R252 R249 R247 R244 R238 R235 47_4 33_4 33_4 10K_4 33_4 33_4 PCLK_DEBUG_R PCLK_PCM_R PCLK_OZ129_R PCI_CLK_SIO_R PCLK_591_R PCLK_ICH_R CG_XIN
1 3 2 0X2 4
475/F_4 475/F_4 CLK_PCIE_3GPLL# 6 CLK_PCIE_3GPLL 6 CLK_MCH_OE# 6 NEW_CLKREQ# 27 CLK_PCIE_NEW 27 CLK_PCIE_NEW# 27 CLK_PCIE_MINI3 25 CLK_PCIE_MINI3# 25 CLK_PCIE_MINI 25 CLK_PCIE_MINI# 25 CLK_PCIE_LAN 26 CLK_PCIE_LAN# 26 CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13 CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12
1 3 4 5 6 7 60 59 10 57 62 8 11 15 19 52 23 29 42 58
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCIF5/ITP_EN XTAL_IN XTAL_OUT USB_48/FSA FSB/TEST/MODE REF0/FSC/TESTSEL VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF
SRC10# SRC10 SRC11/CR#_H SRC11#/CR#_G SRC9 SRC9# SRC7/CR#_F SRC7#/CR#_E SRC6 SRC6# SRC4 SRC4# SRC3/CR#_C SRC3#/CR#_D SRC2/SATA SRC2#/SATA# SRC1/SE1 SRC1#/SE2 SRC0/DOT96 SRC0#/DOT96#
3 1 1 3 1 3 3 1 3 1 3 1
4 0X2 2 2 0X2 4 2 0X2 4 4 0X2 2 4 0X2 2 4 0X2 2
To New Card To MINI3 To MINI1 To LAN
14 CLKUSB_48
R234 CLK_BSEL0 R227 CLK_BSEL1 47_4 2.2K_4
CG_XOUT FSA FSB FSC
To SB To SB
CLK_BSEL2 R243 14 14M_ICH R237
10K_4 47_4
4 IV@0X2 2
DREFCLK DREFCLK#
CKPWRGD/PWRDWN# ICS9LPRS365BGLFT
CK_PWRGD 14
ICS9LPRS365 (ALPRS365K13) RTM875T-606 (AL) PCI2/TME internal PD PCI-3/SRC5_EN internal PD PCI-4/27M_SEL internal PD PCIF-5/ITP_EN internal PD PULL HIGH PULL DOWN +3V R250 10K_4 PCLK_OZ129
&MAIN&:ICS9LPRS365BGLFT QCI:ALPRS365K13 &SECOND&:SLG8SP512TTR: QCI:AL8SP512K05
R246 NO OVERCLOCKING (default) NORMAL RUN PIN37/38 IS PCI_STOP/CPU_STOP PIN 17/18 IS SRC/DOT
PCLK_591 HIGH 27MHz LOW SRC
CLK_PCIE_MINI2&4_R CLK_PCIE_MINI2&4#_R
RP49 RP514
1 3 3 1 1 3 3 1
2 IV@0X2 4 4 EV@0X2 2 2 IV@0X2 4 4 2
CLK_PCIE_MINI2 25 CLK_PCIE_MINI2# 25 CLK_PCIE_MINI4 25 CLK_PCIE_MINI4# 25 DREFSSCLK 6 DREFSSCLK# 6
To MINI2 To MINI4 To NB To VGA Card
PIN37/38 IS SRC5
*10K_4 10K_4
PCI-4/27M_SEL
PIN 17/18 IS 27MHz
DREFSSCLK_R DREFSSCLK#_R PCLK_ICH
PCIF-5/ITP_EN
PIN 46/47 IS CPUITP
PIN 46/47 IS SRC8
*10K_4 10K_4
CLK_MXM 18 CLK_MXM# 18
FREQ. SEL TABLE
Clock Gen I2C
Q507 3 CPU_BSEL0 +1.05V R601 0_4 CLK_BSEL0
R245 10K_4 CGDAT_SMB CGDAT_SMB 17 PCLK_PCM PCLK_591 C225 C219 *33p/50V_4 *33p/50V_4
MCH_BSEL0 6 14,21,25,27 SDATA
*56_4 1K_4
BSEL Frequency Select Table
FSB 0 0 1 1 1 1 0 0
FSA 0 1 1 0 0 1 1 0
Frequency 266Mhz
3 CPU_BSEL1 Q509 R248 10K_4 R228 R226 0_4 *0_4 CLK_BSEL1
C214 C216 C215
15p/50V_4 *33p/50V_4 *33p/50V_4
14M_ICH PCLK_ICH
MCH_BSEL1 6 14,21,25,27 SCLK
133Mhz 166Mhz
CGCLK_SMB 17 PCLK_DEBUG C224 *33p/50V_4
0 0 1 1 1 1
200Mhz 400Mhz Reserved 100Mhz 333Mhz
3 CPU_BSEL2
R598 R232 R593
0_4 *0_4 1K_4
MCH_BSEL2 6
Quanta Computer Inc.
PROJECT : TE1M
Size Document Number
Monday, May 26, 2008
Rev E3D Sheet 2 of 40
H_D#[0..63] 5 H_A#[3..16] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# R32 H_INTR H_NMI H_SMI# T6 T7 T8 T9 T502 T501 T14 T500 T10 0_4
BOM Option Table
H_D#[0..63] 5
Description
H_ADSTB#0 H_REQ#[0..4]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 D2 D22 D3 F6
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK#
H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BREQ# H_IERR# H_INIT# H_LOCK# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
H_ADS# H_BNR# H_BPRI#
U501B H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
ZS2 Default no use this function R46 56_4 +1.05V
DATA GRP 2
ADDR GROUP_0
H_DEFER# 5 H_DRDY# 5 H_DBSY# 5
H_LOCK# 5 L54 H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5 H_HIT# H_HITM# T12 T11 T3 T13 T2 T1 5 5
BK-T_6 H_CPURST# near CPU side 5 5 5 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_CPURST# 5
RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R80 R74 R22 R21
DATA GRP 0
H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5
H_A#[17..35]
XDP/ITP SIGNALS
0_4 SYS_RST#
SYS_RST# 14
PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 C7
H_PROCHOT#_D H_THERMDA H_THERMDC CPU_PM_THRMTRIP#
R81 1K/F_4
H_DSTBN#1 H_DSTBP#1 H_DINV#1 T15 T17 T16 T21 T4 T20 T5
DATA GRP 3
ADDR GROUP_1
Connect it to CPU DBR# is for ITP debug port or CPU interposer (like ICE) to reset the system
DATA GRP 1
H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5 27.4/F_6 54.9/F_4 27.4/F_6 54.9/F_4 ICH_DPRSTP# 6,12,33 H_DPSLP# 12 H_DPWR# 5 H_PWRGD 12 H_CPUSLP# 5 PSI# 33
12 H_A20M# 12 H_FERR# 12 H_IGNNE#
A20M# FERR# IGNNE#
12 12 12 12
H_STPCLK# H_INTR H_NMI H_SMI#
STPCLK# LINT0 LINT1 SMI# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09]
R75 2K/F_4
BCLK[0] BCLK[1] A22 A21
CLK_CPU_BCLK CLK_CPU_BCLK#
CLK_CPU_BCLK 2 CLK_CPU_BCLK# 2 Layout note: H_GTLREF: Zo=55 ohm,L&0.5& 2/3*VCCP+-2% 2 2 2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
GTLREF COMP[0] MISC TEST1 COMP[1] TEST2 COMP[2] TEST3 COMP[3] TEST4 TEST5 DPRSTP# TEST6 DPSLP# TEST7 DPWR# BSEL[0] PWRGOOD BSEL[1] SLP# BSEL[2] PSI#
Penryn_1p0
Layout note: comp0,2: Zo=27.4ohm, L&0.5& comp1,3: Zo=55ohm, L&0.5&
Penryn_1p0
ICH_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# PSI#
Layout note: ICH_DPRSTP# , Daisy Chain (SB&PowerIC&NB&CPU)
Thermal Trip
CPU Thermal monitor
+3V 6,14,33 DELAY_VR_PWRGOOD
R31 FDV301N *10K_4 *BAS316 *51/F_4
Reserve 1K for XDP function
XDP_TDO XDP_TDI XDP_TMS R23 R24 R19 R25 R20 *51/F_4 56_4 54.9/F_4 56_4 56_4
+1.05V R50 200_6 LM86VCC C68 0.1u/10V_4
Q11 22,28 2ND_MBCLK
+1.05V R41 1K_4 R37 56.2/F_4 CPU_PM_THRMTRIP#
R39 100K_4
XDP_TCK XDP_TRST#
2ND_MBCLK#
SCLK SDA ALERT# OVERT#
VCC DXP DXN GND
Q6 MMBT3904
Reserve 1K for XDP function
22,28 2ND_MBDATA
2ND_MBDATA#
R38 *0_4 PM_THRMTRIP#
NS LM95245 PU this pin
PM_THRMTRIP# 6,12 +3V R93 10K_4 THERM_ALERT#_R
No use Thermal trip CPU side still PU 56ohm. Use Thermal trip can share PU at SB side
CPU FAN CTRL
14 THERM_ALERT#
R97 R49 R79
*0_4 10K_4 330_4
ADDRESS: 98H LM95245 : AL
Processor hot
+1.05V No use PROCHOT CPU side still PU 56ohm. Use PROCHOT to optional receiver CPU side PU 68ohm and through isolat 2.2K ohm to receiver side
+3V 32 R95 10K_4 +5V U502 C89 R51 *2.2K_4 *0_4 H_PROCHOT# 33 18 SYSFANON# 28 VFAN R94 2.2u/6.3V_6 0_4 28 FANSIG TH_FAN_POWER C87 10u/10V_8 C90 0.01u/16V_4 C91 *0.01u/16V_4 B2A FAN_CON FANSIG CN504 SYS_SHDN#
THER_SHD# 1 MMBT3904
C62 *1u/16V_6
H_PROCHOT#_D
VO GND /FON GND GND VSET GND
FANPWR = 1.6*VSET
Quanta Computer Inc.
PROJECT : TE1M
Size Document Number
CPU(1/2)- Host Bus
Rev E3D Sheet 3 of 40
Monday, May 26, 2008
BOM Option Table Reference
Description
Need NC 20PCS 10u before A1 BOM released(A0 all stuff)
Place these parts reference to Intel demo board.
U501D VCC_CORE VCC_CORE U501C VCC_CORE
Layout Note: Inside CPU center cavity in 2 rows
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
Penryn_1p0
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
C548 10u/10V_8
C530 10u/10V_8
C37 10u/10V_8
C529 10u/10V_8
C42 10u/10V_8
C533 10u/10V_8
C536 10u/10V_8
C51 10u/10V_8
C61 10u/10V_8
C546 10u/10V_8
C43 10u/10V_8
C60 10u/10V_8
C46 10u/10V_8
C528 10u/10V_8
C527 10u/10V_8
C63 10u/10V_8
C41 10u/10V_8
C45 10u/10V_8
C547 10u/10V_8
C544 10u/10V_8
C52 10u/10V_8
C48 10u/10V_8
C526 10u/10V_8
C38 10u/10V_8
C53 10u/10V_8
C40 10u/10V_8
C545 10u/10V_8
C540 10u/10V_8
C538 10u/10V_8
C531 10u/10V_8
C549 10u/10V_8
C541 10u/10V_8
C537 10u/10V_8
C542 10u/10V_8
C539 10u/10V_8
C550 10u/10V_8
C54 + 330u/2V_7343 +
C55 330u/2V_7343
VCC_CORE Bulk CAPs place to BOT of CPU centeral
Power require
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
Penryn_1p0
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] VCCA[01] VCCA[02] VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
C33 0.1u/10V_4
C65 0.1u/10V_4
C64 0.1u/10V_4
C35 0.1u/10V_4
C34 0.1u/10V_4
C66 0.1u/10V_4
C58 330u/2.5V_7343
VCCP Bulk CAP close to Pin
+VCCA_PROC C71 0.01u/16V_4 C79 10u/10V_8 R76 0_6
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
33 33 33 33 33 33 33
Place 0.01u near pin-B26
VCC_CORE Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
R512 100/F_6
Penryn CPU Power Status and max current table
POWER PLANE S0
VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCCA VCCP O O O O O O O
X X X X X X X
X X X X X X X
VID VID VID VID +1.5V +1.05V +1.05V
47A 50A TBD 67A 130mA 4.5A 2.5A
Standard Voltage CPU SV Design Target Extreme Edition CPU EE Design Target
R511 100/F_6 VCCSENSE 33
VSSSENSE 33
Before VCC Stable After VCC Stable
(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current) (See Penryn EMTS Rev:1.0 Table-3 for VID table)
Quanta Computer Inc.
PROJECT : TE1M
Size Document Number
CPU(2/2)- Power
Rev E3D Sheet
Monday, May 26, 2008
BOM Option Table Reference
3 H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_SWING H_RCOMP F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 C5 E3 U504A H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_SWING H_RCOMP H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_ADS# 3 H_ADSTB#0 3 H_ADSTB#1 3 H_BNR# 3 H_BPRI# 3 H_BREQ# 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 2 CLK_MCH_BCLK# 2 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3 H_A#[35..3] 3
Description
EV&IV diff. BOM
+1.05V_VCCP_GMCH
0.3125*VCCP W:10,S:20 , L&0.5&
R532 221/F_4 H_SWING
R531 100/F_4
C568 0.1u/10V_4
W:10,S:20 , L&0.5&
H_RCOMP R108 24.9/F_4
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
+1.05V_VCCP_GMCH
2/3*VCCP W:10,S:20 , L&0.5&
R534 1K/F_4 H_AVREF R536 2K/F_4 R535 0_4 H_DVREF H_AVREF H_DVREF 3 3 H_CPURST# H_CPUSLP# H_CPURST# H_CPUSLP#
H_REQ#[4..0]
H_CPURST# H_CPUSLP#
H_RS#[2..0]
H_AVREF H_DVREF EV_IV@CANTIGA_1p2
H_CPURST# C802 *0.1u/10V_4
GM PN=& AJSLB940T05 PM PN=& AJSLB970T03
Quanta Computer Inc.
PROJECT : TE1M
Size Date: Document Number
NB (1/7)- HOST
Monday, May 26, 2008 Sheet
Rev E3D 5 of 40
BOM Option Table
U504B T69 T76 T73 T67 T38 T39 T41 T43 T40 MCH_RSVD1 MCH_RSVD2 MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE3 M_CKE4 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMP M_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT MCH_SM_DRAMRST# DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# CLK_PCIE_3GPLL CLK_PCIE_3GPLL#
Description
INT VGA EXT VGA INT HDMI EV&IV diff. BOM
DDR CLK/ CONTROL/COMPENSATION
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4 M_CKE0 M_CKE1 M_CKE3 M_CKE4 M_CS#0 M_CS#1 M_CS#2 M_CS#3 16,17 16,17 16,17 16,17 16,17 16,17 16,17 16,17
17 17 17 17 17 17 17 17
EV@ GM PN=& AJSLB940T05 PM PN=& AJSLB970T03 IHM@ EV_IV@
MCH_RSVD14 MCH_RSVD15 MCH_RSVD17
T24 B31 M1 AY21 B2 BG23 BF23 BH18 BF18
19 INT_LVDS_PWM 19 INT_LVDS_BLON INT_LVDS_PWM INT_LVDS_BLON L_CTRL_CLK L_CTRL_DATA INT_LVDS_EDIDCLK INT_LVDS_EDIDDATA
L&0.5& , If PCIE not support still connect to +VCC_PEG
+1.05V_VCC_PEG
RSVD15 RSVD17 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
EXP_A_COMPX
MCH_RSVD20
T27 T54 T51 T506 T42
MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25
M_ODT0 16,17 M_ODT1 16,17 M_ODT2 16,17 M_ODT3 16,17
19 INT_LVDS_EDIDCLK 11,19 INT_LVDS_EDIDDATA
19 INT_LVDS_DIGON T85
19 INT_TXLCLKOUT19 INT_TXLCLKOUT+ SM_DRAMRST# only for DDR3.(DDR2 NC). T65 T71 19 INT_TXLOUT019 INT_TXLOUT119 INT_TXLOUT2T74 19 INT_TXLOUT0+ 19 INT_TXLOUT1+ 19 INT_TXLOUT2+ T78 T84 T83 T75 T86 T79 T82 T72 T81
INT_LVDS_DIGON LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL INT_TXLCLKOUTINT_TXLCLKOUT+ INT_TXUCLKOUTINT_TXUCLKOUT+ INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2INT_TXLOUT3INT_TXLOUT0+ INT_TXLOUT1+ INT_TXLOUT2+ INT_TXLOUT3+ INT_TXUOUT0INT_TXUOUT1INT_TXUOUT2INT_TXUOUT3INT_TXUOUT0+ INT_TXUOUT1+ INT_TXUOUT2+ INT_TXUOUT3+
PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 C_PEG_TXN0 C_PEG_TXN1 C_PEG_TXN2 C_PEG_TXN3 C_PEG_TXN4 C_PEG_TXN5 C_PEG_TXN6 C_PEG_TXN7 C_PEG_TXN8 C_PEG_TXN9 C_PEG_TXN10 C_PEG_TXN11 C_PEG_TXN12 C_PEG_TXN13 C_PEG_TXN14 C_PEG_TXN15 C_PEG_TXP0 C_PEG_TXP1 C_PEG_TXP2 C_PEG_TXP3 C_PEG_TXP4 C_PEG_TXP5 C_PEG_TXP6 C_PEG_TXP7 C_PEG_TXP8 C_PEG_TXP9 C_PEG_TXP10 C_PEG_TXP11 C_PEG_TXP12 C_PEG_TXP13 C_PEG_TXP14 C_PEG_TXP15 C690 C692 C688 C686 C654 C681 C663 C656 C644 C646 C673 C649 C678 C651 C661 C683 C691 C693 C689 C687 C655 C682 C664 C657 C645 C642 C674 C650 C679 C652 C662 C684
PEG_RXN[15:0]
T68 T70 T66 T80
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
AL34 AK34 AN35 AM35
ME_JTAG_TCK ME_JTAG_TDI ME_JTAG_TDO ME_JTAG_TMS
PEG_CLK PEG_CLK#
CLK_PCIE_3GPLL 2 CLK_PCIE_3GPLL# 2
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN[3:0]
DMI_TXP[3:0]
2 MCH_BSEL0 2 MCH_BSEL1 2 MCH_BSEL2
11 MCH_CFG_5 11 MCH_CFG_6 11 MCH_CFG_7 11 MCH_CFG_9 11 MCH_CFG_10 11 MCH_CFG_12 11 MCH_CFG_13
11 MCH_CFG_16
T47 T44 T49 T59
GRAPHICS VID
11 MCH_CFG_19 11 MCH_CFG_20
MCH_BSEL0 MCH_BSEL1 MCH_BSEL2 MCH_CFG_3 MCH_CFG_4 MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 MCH_CFG_8 MCH_CFG_9 MCH_CFG_10 MCH_CFG_11 MCH_CFG_12 MCH_CFG_13 MCH_CFG_14 MCH_CFG_15 MCH_CFG_16 MCH_CFG_17 MCH_CFG_18 MCH_CFG_19 MCH_CFG_20
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PCI-EXPRESS
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
DREFCLK 2 DREFCLK# 2 DREFSSCLK 2 DREFSSCLK# 2
PEG_RXP[15:0]
ME JTAG CFG
DMI_RXN[3:0]
TV IF (Disable)
INT_TV_COMP INT_TV_Y/G INT_TV_C/R INT_TV_RNT
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC TV_RTN
DMI_RXP[3:0]
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
TV_DCONSEL_0 TV_DCONSEL_1
TV_DCONSEL_0 TV_DCONSEL_1
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4
PEG_TXN0 PEG_TXN1 PEG_TXN2 PEG_TXN3 PEG_TXN4 PEG_TXN5 PEG_TXN6 PEG_TXN7 PEG_TXN8 PEG_TXN9 PEG_TXN10 PEG_TXN11 PEG_TXN12 PEG_TXN13 PEG_TXN14 PEG_TXN15 PEG_TXP0 PEG_TXP1 PEG_TXP2 PEG_TXP3 PEG_TXP4 PEG_TXP5 PEG_TXP6 PEG_TXP7 PEG_TXP8 PEG_TXP9 PEG_TXP10 PEG_TXP11 PEG_TXP12 PEG_TXP13 PEG_TXP14 PEG_TXP15
PEG_TXN[15:0]
14 PM_SYNC# 3,12,33 ICH_DPRSTP# 17 PM_EXTTS#0 17 PM_EXTTS#1 3,14,33 DELAY_VR_PWRGOOD 13 PLT_RST#_NB 3,12 PM_THRMTRIP# 14,33 PM_DPRSLPVR
PM_EXTTS#0 PM_EXTTS#1
R126 R533 R183 R178 R207 R114 R120 R138
0_4 0_4 0_4 0_4 0_4 100_4 *0_4 0_4
PM_SYNC#_R ICH_DPRSTP#_R PM_EXTTS#0_1_EC_R TS#DIMM0_1_R RST_IN#_MCH THRMTRIP#_R DPRSLPVR_R
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
20 INT_CRT_BLU 20 INT_CRT_GRN 20 INT_CRT_RED
INT_CRT_BLU INT_CRT_GRN INT_CRT_RED CRT_IRTN
E28 G28 J28 G29 H32 J32 J29 E29 L29
PEG_TXP[15:0] 18
CRT_BLUE CRT_GREEN CRT_RED CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
20 INT_CRT_DDCCLK 20 INT_CRT_DDCDAT 20 INT_HSYNC 20 INT_VSYNC
INT_HSYNCR163 INT_VSYNCR165
INT_CRT_DDCCLK INT_CRT_DDCDAT IV@30.1/F_4 HSYNC_G CRTIREF IV@30.1/F_4 VSYNC_G
NB Thermal trip pin No use Thermal trip NB side can NC.(NB has ODT)
PM_DPRSTP# The Daisy chain topology should be routed from ICH9M to IMVP , then to (G)MCH and CPU, in that order.
T512 T513 T516 T515 T511 T89 T514 T510 T88 T509 T508 T507 T34 T37 T32 T36 T35 T30 T33 T22 T28 T31 T29 T26 T23
TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16 TP_MCH_NC17 TP_MCH_NC18 TP_MCH_NC19 TP_MCH_NC20 TP_MCH_NC21 TP_MCH_NC22 TP_MCH_NC23 TP_MCH_NC24 TP_MCH_NC25
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
CL_CLK0 CL_DATA0 MPWROK CL_RST#0 MCH_CLVREF_R
CL_CLK0 14 CL_DATA0 14 MPWROK 14 CL_RST#0 14
HSYNC/VSYNC serial R place close to NB
For IV @ Connect to 30.1ohm For EV@ NC
EV_IV@CANTIGA_1p2
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN#
N28 M28 G36 E36 K36 H36 B12
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLK_MCH_OE# MCH_ICH_SYNC#
DDPC_CTRL for HDMI port C SDVO_CTRL for HDMI port B
DDPC_CTRLDATA 11 SDVO_CTRLCLK 21 SDVO_CTRLDATA 11,21 CLK_MCH_OE# 2 MCH_ICH_SYNC# 14
UMA iHDMI I/F
B28 B30 B29 C29 A28
HDA_BIT_CLK_HDMI HDA_RST#_HDMI HDA_SDIN_HDMI HDA_SDOUT_HDMI HDA_SYNC_HDMI HDA_BIT_CLK_HDMI 12 HDA_RST#_HDMI 12 HDA_SDIN_HDMI 12 HDA_SDOUT_HDMI 12 HDA_SYNC_HDMI 12 NOTE: If (G)MCH's HD Audio signals are connected to ICH9M for iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be only on 1.5V. These power pins on ICH9M can be supplied with 3.3V if and only if (G)MCH's HDA is not connected to ICH9M. Consequently, only 1.5V audio/modem codecs can be used on the platform. PEG_RXP3
R200 IV@0_4 Port-B_HPD# Port-B_HPD# 21
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
C_PEG_TXP0 C_PEG_TXN0 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP3 C_PEG_TXN3
C680 C672 C671 C670 C669 C668 C667 C666
IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4 IHM@0.1u/10V_4
TMDSB_DATA2 TMDSB_DATA2# TMDSB_DATA1 TMDSB_DATA1# TMDSB_DATA0 TMDSB_DATA0# TMDSB_CLK TMDSB_CLK#
TMDSB_DATA2 21 TMDSB_DATA2# 21 TMDSB_DATA1 21 TMDSB_DATA1# 21 TMDSB_DATA0 21 TMDSB_DATA0# 21 TMDSB_CLK 21 TMDSB_CLK# 21
EV_IV@CANTIGA_1p2
Check list note : CL_REF=0.35V
SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.
&Checklist ver0.8& If TSATN# is not used, then it must be terminated with a 56-? pull-up resistor to VCCP.
TSATN# 56_4 R537
IV&EV Dis/Enable LVDS setting(See DG 1.0 P190 Table 103)
+1.05V R190 IV@0_4 LVDS_VREFH LVDS_VREFL
For IV @ 0ohm For EV@ NC For IV @ 2.37K/F For EV@ NC For IV @ 10K For EV@ NC
R180 1K/F_4 MCH_CLVREF_R SM_VREF
+SMDDR_VREF +3V R563 IV@2.37K/F_4 LVDS_IBG
+1.8VSUS_GMCH
CLK_MCH_OE# PM_EXTTS#0
10K_4 10K_4 10K_4
R172 R184 R179 +3V R154 R155 IV@10K_4 IV@10K_4 L_CTRL_CLK L_CTRL_DATA
C164 0.1u/10V_4
R181 511/F_6 R205 10K/F_4 PM_EXTTS#1
IV&EV Dis/Enable CRT setting(See DG 1.0 P190 Table 103)
Dis TV/En CRT( See DG1.0 P208 Table 118)
499/F_4 R176 R177 *EV@0_4 *EV@0_4 INT_CRT_DDCCLK INT_CRT_DDCDAT
SM_PWROK only for DDR3.(DDR2 PD only)
+1.8VSUS_GMCH +1.8VSUS_GMCH +1.8VSUS_GMCH R553 1K/F_4 C585 R551 R547 80.6/F_4 M_RCOMP M_RCOMP# R545 3.01K/F_4 *20/F_4 SM_PWROK SM_RCOMP_VOL R186 10K/F_6 R157 EV_IV@1K/F_4 CRTIREF 0.01u/16V_4 2.2u/6.3V_6 SM_RCOMP_VOH C589 R194 *12K/F_4 HWPG_1.8V 28,35 R162 R164 EV@0_4 EV@0_4 HSYNC_G VSYNC_G
For IV @ NC For EV@ 0ohm to GND or NC For IV @ NC For EV@ 0ohm to GND
R142 R143 R144
EV_IV@75_4 EV_IV@75_4 EV_IV@75_4
INT_TV_COMP INT_TV_Y/G INT_TV_C/R
For IV @ 75ohm to GND For EV@ 0ohm to GND
TV_DCONSEL_0 TV_DCONSEL_1
For IV @ 0ohm to GND For EV@ 0ohm to GND
R159 R160 R161
EV_IV@150/F_4 INT_CRT_BLU EV_IV@150/F_4 INT_CRT_GRN EV_IV@150/F_4 INT_CRT_RED
For IV @ Connect to 150ohm/F For EV@ Connect to 0ohm GND IV&EV Dis/Enable PLL setting(See DG 1.0 P190 Table 103)
DREFCLK DREFCLK# DREFSSCLK DREFSSCLK# R561 R562 R197 R198 EV@0_4 EV@0_4 EV@0_4 EV@0_4
R548 *20/F_4
R546 80.6/F_4
R550 1K/F_4
C583 0.01u/16V_4
C584 2.2u/6.3V_6
Quanta Computer Inc.
For IV @ NC For EV@ 0ohm to GND
For IV @ Connect to 1.02K/F For EV@ Connect to 0ohm GND
PROJECT : TE1M
Size Document Number
Layout Note :See DG1.0 P180
NB (2/7)- VGA, MDI
Date: Friday, June 13, 2008
Rev E3D Sheet 6 of 40
BOM Option Table Reference
EV_IV@ GM PN=& AJSLB940T05 PM PN=& AJSLB970T03
17 M_B_DQ[63:0] 17 M_A_DQ[63:0]
Description
EV&IV diff. BOM
U504D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 EV_IV@CANTIGA_1p2 SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 BB20 BD20 AY20 M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_RAS# M_A_CAS# M_A_WE# M_A_BS#0 16,17 M_A_BS#1 16,17 M_A_BS#2 16,17 M_A_RAS# 16,17 M_A_CAS# 16,17 M_A_WE# 16,17 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
U504E SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 EV_IV@CANTIGA_1p2 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# BC16 BB17 BB33 AU17 BG16 BF14 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_RAS# M_B_CAS# M_B_WE# M_B_BS#0 16,17 M_B_BS#1 16,17 M_B_BS#2 16,17 M_B_RAS# 16,17 M_B_CAS# 16,17 M_B_WE# 16,17
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_A[14:0] 16,17
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS[7:0] 17
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7:0] 17
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
M_B_DM[7:0] 17
M_B_DQS[7:0] 17
M_A_DQS#[7:0] 17
M_B_DQS#[7:0] 17
M_B_A[14:0] 16,17
Quanta Computer Inc.
PROJECT : TE1M
Size Date:
Document Number
NB (3/7)- DDRII
Monday, May 26, 2008
Rev E3D Sheet 7 of 40
BOM Option Table Reference
IV@ GM PN=& AJSLB940T05 PM PN=& AJSLB970T03
+1.8VSUS_GMCH +1.8VSUS_GMCH +1.05V_VCC_GMCH
Description
INT VGA EXT VGA EV&IV diff. BOM
EV@ EV_IV@
+1.8VSUS R149 0_1206 +VGFX_CORE_INT U504G C598 10u/6.3V_8 C594 10u/6.3V_8 C122 0.1u/10V_4 + C156 330u/2.5V_7343
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35
+1.05V_VCC_GMCH
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13
+VGFX_CORE_INT
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
EV_IV@CANTIGA_1p2
+VGFX_CORE_INT
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
Close to GMCH
+1.05V_VCC_GMCH R113 + 0_1206
C148 0.1u/10V_4
C162 0.22u/6.3V_4
C143 0.22u/6.3V_4
C157 22u/6.3V_8
C126 330u/2.5V_7343
Close to GMCH
+VGFX_CORE_INT +1.05V
See Page 9 EV&IV table
C137 IV@0.47u/6.3V_4 C131 IV@1u/16V_6 C128 IV@10u/10V_8 C132 IV@10u/6.3V_8 C124 IV@0.1u/10V_4 C130 R136 IV@0.1u/10V_4 EV@0_6 EV@0_6 R137 R148
+VGFX_CORE_INT
Place close to the GMCH and different location
VCC GFX NCTF
+ C104 IV@330u/2.5V_7343
+ C103 IV@330u/2.5V_7343
Close to GMCH
NB Power Status and max current table(1/3)
POWER PLANE
VCC(EXT_VGA) VCC(INT_VGA) VCC_AXG VCC_SM(800) VCC_SM(Standby)
+1.05V +1.05V +1.05V +1.8VSUS +1.8VSUS
2178mA 2899mA 8700mA 3A 1mA
Graphics Core (DDRII-667) 2.6A Self Refresh during S3
(See NB EDS Rev:1.0 Section 10.1 for max current) (See NB EDS Rev:1.0 Section 12.2 for DC voltage)
Close to each pins 1.8V Internal connect to power
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AV44 BA37 AM40 AV21 AY5 AM10 BB13
C123 0.1u/10V_4 C117 0.1u/10V_4 C114 0.22u/6.3V_4 C135 0.22u/6.3V_4 C170 0.47u/10V_6 C153 1u/16V_6 C175 1u/16V_6
IV@10/F_6 IV@10/F_6
VCC_AXG_SENSE VSS_AXG_SENSE
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially 2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm and VSS_AXG_SENSE PD with 10ohm for Intel suggest
EV_IV@CANTIGA_1p2
Quanta Computer Inc.
PROJECT : TE1M
Size Document Number
NB (4/7)- VCC, NCTF
Rev E3D Sheet 8 of 40
Monday, May 26, 2008
BOM Option Table Reference
+3V_A_TV_CRT +3V L506 C575 IV@10u/10V_8 IV@BLM18PG181SN1D_6 C580 IV@0.1u/10V_4 C579 IV@0.01u/16V_4 R549 EV@0_4 +3V_A_TV_CRT
Description
INT VGA EXT VGA INT HDMI EV&IV diff. BOM
+3V_A_DAC_BG
C581 IV@0.1u/10V_4
+3V_A_CRT_DAC
C582 IV@0.01u/16V_4
EV@ IHM@ EV_IV@
IV@10uh_8 R565 C629 IV@220u/2.5V_7343
+1.05VM_DPLLA
R203 C187 EV@0_4
GM PN=& AJSLB940T05 PM PN=& AJSLB970T03
C619 EV@0_4 IV@0.1u/10V_4
C166 IV@220u/2.5V_7343
IV@0.1u/10V_4
+1.05V_VCCP_GMCH
+1.05VM_DPLLB
+1.05V R104 0_6
U504H VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
+1.05V_VCCP_GMCH
C115 0.47u/6.3V_4 C564 2.2u/6.3V_6 C566 4.7u/10V_6 C562 4.7u/10V_6
+1.05VM_MCH_PLL2
0_6 C108 4.7u/10V_6 C112 0.1u/10V_4
+1.05VM_HPLL
+3V_A_CRT_DAC
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
330u/2.5V_7343
VCCA_DAC_BG VSSA_DAC_BG
BLM18PG181SN1D_6
+1.05VM_MPLL
+1.05VM_DPLLA +1.05VM_DPLLB +1.05VM_HPLL
F47 L48 AD1 AE1
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
+3V_A_DAC_BG
+1.05VM_AXF
C569 1u/6.3V_4
L503 C572 *10u/10V_8
R100 C110 0.1u/10V_4
*0.5/F_6 C96
+1.05VM_MPLL_RC
*22u/6.3V_8 C621 IV@
+1.05VM_MPLL
+1.8VSUS_TXLVDS
+1.8VSUS_VCC_SM_CK
C576 1/F_4 R538
+1.8VSUS_GMCH
0_8 C617 0.1u/10V_4
+1.5V_VCCA_PEG_BG AD48
VCCA_PEG_BG
0_6 C134 C129 10u/6.3V_8 C125 4.7u/10V_6 C121 1u/6.3V_4
+1.05VM_A_SM
*10u/6.3V_8 100u/6.3V_3528
+1.8VSUS_SMCK_RC
+1.05VM_PEGPLL
+1.05VM_A_SM
0.1u/10V_4 C570 10u/10V_8
VCCA_PEG_PLL
+1.05VM_A_SM_CK
C139 *2.2u/6.3V_6 C138 10u/6.3V_8 C136 0.1u/10V_4
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9
+1.8VSUS_TXLVDS
R564 EV@0_4 C622 IV@
IV@0.1uh_8
C626 IV@10u/6.3V_8 +1.05V
+1.05VM_A_SM_CK +3V R543 IV@0_6
+3V_TV_DAC
C578 IV@0.1u/10V_4 C577 IV@0.01u/16V_4 R544 EV@0_4
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8
D502 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 B22 B21 A21 +1.05VM_AXF
CH751H-40PT
R557 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 BF21 BH20 BG20 BF20 +1.8VSUS_VCC_SM_CK
+3V_VCC_HV
C599 0.1u/10V_4
IHM@0_6 C596 IHM@0.1u/10V_4
+1.5V_VCC_HDA
+3V_TV_DAC
FOR iHDMI HDA I/F only
R556 EV@0_4
IF iHDMI not used,HDA connect ot GND(DG1.0 P277)
+1.5V_VCC_HDA
VCC_TX_LVDS VCCA_TV_DAC_1 VCCA_TV_DAC_2 VCC_HV_1 VCC_HV_2 VCC_HV_3
K47 C35 B35 A35
+1.8VSUS_TXLVDS
+3V_VCC_HV
+1.05V_VCC_PEG
+1.05V_VCC_PEG
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 V48 U48 V47 U47 U46 +1.05V_VCC_PEG 4.7u/10V_6 10u/6.3V_8 220u/2.5V_7343
+1.5V_TVDAC +1.5V_QDAC
M25 L28 AF1 AA47
VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL
+1.5V_TVDAC
C587 0.1u/10V_4 C588
+1.05VM_MCH_PLL2
0.01u/16V_4
+1.05VM_PEGPLL
C102 +1.8VSUS_DLVDS 0.1u/10V_4
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
AH48 AF48 AH47 AG47
+1.05V_VCC_DMI
+1.05V_VCC_DMI
C616 0.1u/10V_4
R211 C625 *10u/10V_8
+1.05V_VCC_PEG
VCCD_LVDS_1 VCCD_LVDS_2
IV@BLM18PG181SN1D_6
+1.5V_QDAC
C592 IV@0.1u/10V_4 C591 IV@0.01u/16V_4 R554 EV_IV@CANTIGA_1p2 EV@0_4
VTTLF1 VTTLF2 VTTLF3
A8 L1 AB2 C107 0.47u/6.3V_4 C105 0.47u/6.3V_4 C113 0.47u/6.3V_4
C586 IV@10u/6.3V_8
NB Power Status and max current table(2/3)(NB left side)
POWER PLANE
+1.05V L512 BLM18PG181SN1D_6 C623 0.1u/10V_4 C618 0.1u/10V_4
EXT&INT VGA Power Plane Option table
POWER PLANE
VCCA_CRT_DAC VCCD_LVDS VCC_TX_LVDS VCCA_LVDS VCCD_TVDAC VCCA_TV_DAC VCCD_QDAC VCCA_DAC_BG VCC_AXG
NB Power Status and max current table(3/3)(NB Right side)
POWER PLANE
VTT VCCA_AXF VCC_SM_CK(800) VCC_TX_LVDS VCC_HV
O O O O O O O O O O O O O O O O O O
X X X X X X O X X X X X X X X X X O
X X X X X X X X X X X X X X X X X X
+3.3V +3.3V +1.05V +1.05V +1.05V +1.05V +1.8VSUS +1.5V +1.05V +1.05V +1.05V +3.3V +1.5V +1.5V +1.5V +1.05V +1.05V +1.8VSUS
73mA 5mA 64.8mA 64.8mA 24mA 139.2mA 13.2mA 414uA 50mA 720mA 26mA 79mA 50mA 35mA 125uA 157mA 50mA 60mA
GND GND GND GND +1.5V GND GND GND GND GND GND GND GND
+3V +1.8VSUS +1.8VSUS +1.8VSUS +1.5V +3V +1.5V +3V +1.05V +1.05V +1.05V +1.05V +1.5V
DR1 DR2 DR3 DR4
O O O O O O O
X X O O X X X
X X X X X X X
+1.05V +1.05V +1.8VSUS +1.8VSUS +3V +1.05V +1.05V
852mA 322mA 124mA 119mA 106mA 1782mA 456mA
FSB at 1067MHz
+1.05VM_PEGPLL
VCCA_CRT_DAC VCCA_DAC_BG VCCA_DPLLA VCCA_DPLLB VCCA_HPLL
(DDRII-667) 120mA
1/F_4 C628 10u/10V_8
+1.05VM_PEGPLL_RC
VCCA_MPLL VCCA_LVDS VCCA_PEG_BG VCCA_PEG_PLL VCCA_SM(DDRII-800)
DR5 DR6 DR7 DR8 Page 8 DR9 Page 8 DR10 DR11 DR12 For iHDMI
VCC_PEG VCC_DMI
(See NB EDS Rev:1.0 Section 10.1 for max current) (See NB EDS Rev:1.0 Section 12.2 for DC voltage)
(DDRII-667) 480mA (DDRII-667) 24mA
VCC_AXG_NCTF VCCA_DPLLA VCCA_DPLLB VCC_HDA
+1.8VSUS_DLVDS
C602 IV@1u/6.3V_4 R559 EV@0_4
VCCA_SM_CK(800) VCCA_TV_DAC VCC_HDA VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS
EXT VGA-&Disable TV/CRT/LVDS/HDMI(See DG 1.0 P190 Table 103) INT VGA-&Disable TV/Enable CRT( See DG1.0 P208 Table 118) INT VGA-&Disable HDMI(See DG 1.0 P277 section 3.10.4)
Size Document Number
Quanta Computer Inc.
PROJECT : TE1M
NB (5/7)- POWER
Date: Monday, May 26, 2008
Rev E3D Sheet 9 of 40
BOM Option Table
U504I U504J
VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AJ6 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 A47
MCH_VSS_351 MCH_VSS_352 MCH_VSS_353 MCH_VSS_354 MCH_VSS_355 R152 R156 R147 R169 R109 0_4 0_4 0_4 0_4 0_4
Description
EV&IV diff. BOM
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_6 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 NC_43
GM PN=& AJSLB940T05 PM PN=& AJSLB970T03
EV_IV@CANTIGA_1p2 EV_IV@CANTIGA_1p2
Quanta Computer Inc.
PROJECT : TE1M
Size Date: Document Number
NB (6/7)- VSS
Monday, May 26, 2008
Rev E3D Sheet 10 of 40
North Bridge Strap Pin Configuration Table
(See DG 1.0 P295 Table 184) (See NB EDS 1.0 P187 Table 74)
BOM Option Table Reference
Description
Internal TPM
Strap description
FSB Frequency Select Reserved DMI X2 Select iTPM Host Interface ME TLS Confidentiality Reserved
PCI Express Graphics Lane Reversal
Configuration
[000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz
PU&4.02K& PD &2.21K&
See Page 2 FSB selection table
CFG[2:0] CFG[4:3] CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG[15:14] CFG16 CFG[18:17]
0 = DMI X2 1 = DMI X4(Default) 0 = iTPM Host Interface is enabled 1 = iTPM Host Interface is disabled(Default)
0 = AMT Firmware will use TLS cipher suite with no confidentiality 1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)
6 MCH_CFG_5
*4.02K/F_4
6 MCH_CFG_6
*iTPM@10K/F_4
6 MCH_CFG_7
*4.02K/F_4
0 = Reverse Lanes 1 = Normal operation(Default) 0 = Enabled 1 = Disabled (Default)
6 MCH_CFG_9
*4.02K/F_4
PCIE Loopback enable Reserved ALLZ XOR Reserved FSB Dynamic ODT Reserved DMI Lane Reversal
6 MCH_CFG_10
*4.02K/F_4
0 = ALLZ mode enable 1 = disable(Default) 0 = XOR mode enable 1 = disable(Default)
6 MCH_CFG_12
*4.02K/F_4
6 MCH_CFG_13
*4.02K/F_4
0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)
6 MCH_CFG_16
*4.02K/F_4
0 = Normal (Default) 1 = Lanes Reversed 0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is operational (Default) 1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating simultaneously via PEG port 0 = No SDVO/HDMI/DP Device Present(Default) 1 = SDVO/HDMI/DP Device present 0 = LFP Disable(Default) 1 = LFP Card PPCIE disable 0 = Digital display(HDMI/DP) device absent(Default) 1 = Digital display(HDMI/DP) device present
6 MCH_CFG_19
*4.02K/F_4
Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIE
6 MCH_CFG_20
*4.02K/F_4
SDVO_CTRLDATA
SDVO Present Local Flat Panel(LFP) Present Digital Display Present
6,21 SDVO_CTRLDATA
Reference PAGE21 R185
L_DDC_DATA
DDPC_CTRLDATA
6,19 INT_LVDS_EDIDDATA
6 DDPC_CTRLDATA
Enable iTPM Table
MCH_CFG_6 SPI_MOSI CLGPIO5
PD 10K to GND PU 20K to +3V_S5 PU 10K to +3V_S5
NB Strap pin SB Strap pin SB Strap pin
Size Date: Document Number
Quanta Computer Inc.
PROJECT : TE1M
NB (7/7)- STRAP PIN
Monday, May 26, 2008
Rev E3D Sheet 11 of 40
RTC CRYSTAL
C243 15p/50V_4 CLK_32KX1 CLK_32KX1 CLK_32KX2 32.768KHZ Y6 R268 10M_6 CLK_32KX2 ICH_INTVRMEN RTC_RST# SRTC_RST# SM_INTRUDER# U512A
Layout note: DPRSTP# , Daisy Chain (SB&Power&NB&CPU)
BOM Option Table Reference
Description
LDRQ0/1# : Internal PU
C23 C24 A25 F20 C22 B22 A22 E25 C13 RTCX1 RTCX2 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M# K5 K4 L6 K2 K3 J3 J1 N7 AJ27 AJ25 AE23 AJ26 AD22 AF25 AE22 AG25 L3 AF23 AF24 AH27 AG26 AG27 AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7
LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ#0 LDRQ#1 GATEA20 H_A20M# H_DPRSTP#_R H_DPSLP#_R H_FERR#_R H_PWRGD H_IGNNE# H_INIT# H_INTR RCIN# H_NMI H_SMI#_R H_STPCLK# H_THERMTRIP_R ICH_TP12 SATA_RXN4_C SATA_RXP4_C SATA_TXN4_C SATA_TXP4_C SATA_RXN5 SATA_RXP5 SATA_TXN5 SATA_TXP5 CLK_PCIE_SATA# CLK_PCIE_SATA T524 T525 T520 T519 CLK_PCIE_SATA# 2 CLK_PCIE_SATA 2 T517 T528 LDRQ#1 25 GATEA20 28 H_A20M# 3 R645 R275 R642 H_PWRGD 3 H_IGNNE# H_INIT# 3 H_INTR 3 RCIN# 28 H_NMI 3 R270 0_4 H_SMI# 3 +1.05V_ICH_IO 0_4 0_4 56_4 ICH_DPRSTP# H_DPSLP# 3 3,6,33 LAD0 LAD1 LAD2 LAD3 25,28 25,28 25,28 25,28
+1.05V_ICH_IO
RTCRST# SRTCRST# INTRUDER# INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
LFRAME# 25,28 R647 *56_4 R285 *56_4 +1.05V_ICH_IO
LAN / GLAN CPU
RESET JUMP
F14 G13 D14 D13 D12 E13
ICH_GPIO56 G1 *SHORT_ PAD
DPRSTP# DPSLP# FERR# CPUPWRGD IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
R640 56_4 H_FERR#
An RC delay circuit with a time delay in the range of 18 ms to 25 ms should be provided 20K_6 C640 1u/6.3V_4 RTC_RST#
B10 B28 B27 AF6 AH4 AE7 AF4 AG4 AH3 AE5 AG5 AG7 AE8 AG8 AJ16 AH16 AF17 AG17 AH13 AJ13 AG14 AF14
GLAN_COMP HDA_BIT_CLK_R HDA_SYNC_R HDA_RST#_R
R266 56_4 R263 *0_4 PM_THRMTRIP#
H_STPCLK# 3 R639 56_4 H_THERMTRIP_RR PM_THRMTRIP# 3,6
29 ACZ_SDIN0
C259 1u/6.3V_4
G2 *SHORT_ PAD
ACZ_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 T105 HDA_SDOUT_R T522 T102 ICH_GPIO33 ICH_GPIO34 SATA_LED# SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
TP12 SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP
Layout note: PU R needs to placed within 2& of ICH9-M, series R must be placed within 2&of PU R w/o stub.
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#
+VCCRTC R576 R295 1M_4 332K/F_4 SM_INTRUDER# ICH_INTVRMEN
(DG 1.0 Table-292)
Internal VRM enabled for VccSus1_05, VccSus1_5, VccCL1_5, VccLAN1_05 and VccCL1_05.
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
ICH9M REV 1.0
GATEA20 R343 RCIN# R370
8.2K_4 10K_4
SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C
SATA_RBIAS_PN R675
To SATA HDD
22 22 22 22 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 C738 C737 C734 C735
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
+3V_S5 R338 10K_4 ICH_GPIO56
SATA_RBIAS_PN&0.5&.Avoid routing next to clock/high speed signals
To SATA ODD
+1.5V_PCIE_ICH R257 24.9/F_4 GLAN_COMP 24.9 Ohm pull up to 1.5V for GLAN_COMPI/O is required, no matter intel LAN is used or not.
22 22 22 22
SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1
SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1
C746 C743 C739 C740
SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C
27 SATA_RXN4 27 SATA_RXP4 SATA_RXN4 SATA_RXP4 SATA_TXN4 SATA_TXP4 C613 C611 C799 C798
SATA_RXN4_C SATA_RXP4_C SATA_TXN4_C SATA_TXP4_C
27 SATA_TXN4 27 SATA_TXP4
HD Audio I/F(CODEC& iHDMI)
R693 HDA_SDIN2 HDA_SDIN1 R705 R706 *IHM@0_4 HDA_SDOUT_R IHM@0_4 HDA_SDIN_HDMI HDA_RST#_HDMI ACZ_RST#_AUDIO 6 R708 R676 HDA_RST#_R R680 IHM@33_4 33_4 6 29 R683 HDA_BIT_CLK_R R679 IHM@33_4 33_4 HDA_BIT_CLK_HDMI BIT_CLK_AUDIO 29 6 HDA_SYNC_R R707 IHM@33_4 33_4 HDA_SYNC_HDMI ACZ_SYNC_AUDIO 6 29 R691 33_4 IHM@33_4 HDA_SDOUT_HDMI ACZ_SDOUT_AUDIO 6 29
RTC BATTERY
+3VPCU D508 D512 CH500H-40 CH500H-40 C648 1u/10V_6 R588 1K_4 +5VPCU +VCCRTC
South Bridge Strap Pin (1/3)
HDA_DOCK_EN/ GPIO33
Strap description
Flash Descriptor Security Override Strap PCI Express Lane Reversal (Lanes 1-4) XOR Chain Entrance
XOR Chain Entrance /PCI Express* Port Config 1 bit 1(Port 1-4)
Configuration
0 = The Flash Descriptor Security will be overridden. 1 = The security measures defined in the Flash Descriptor will be in effect
Q505 MMBT.8K/F_4 RTC_N03 R587 15K_4
This strap should only be enabled in manufacturing environments using an external pull-up resistor.
Internal PU
ICH_TP3 HDA_SDOUT
Description RSVD Enter XOR Chain
Normal opration(Default) Set PCIE port config bit 1
0 0 PWROK 1 1
Quanta Computer Inc.
PROJECT : TE1M
Size Date:
HDA_SDOUT_R
+3V_HDA_IO_ICH
Document Number
SB (1/4)- HOST
Monday, May 26, 2008
Rev E3D Sheet 12 of 40
BOM Option Table
PCI/PCI-E/USB/DMI/SPI
23,24 AD[0..31] U512B AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 R373 R374 R372 R387 0_4 *0_4 0_4 *0_4 INTA#_R INTB#_R INTC#_R INTD#_R D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 J5 E1 J6 C4 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD# ICH9M REV 1.0 U512D C249 C248 0.1u/10V_4 0.1u/10V_4 PCIE_TXN1_C PCIE_TXP1_C REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 C14 D4 R2 REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# CBE0# CBE1# CBE2# CBE3# IRDY# PAR PCIRST# DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME# PLT_RST-R# PCLK_ICH PCI_PME# REQ0# GNT0# REQ1# GNT1# T103 24 24 23 23 27 27 27 27 25 25 25 25 23,24 23,24 23,24 23,24 23,24 23,24 23,24 23,24 23 23 23,24 23,24 23,24 25 25 25 25 25 25 25 25 26 26 26 26 25 25 25 25 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5 PCIE_RXN6 PCIE_RXP6 PCIE_TXN6 PCIE_TXP6 N29 N28 P27 P26 L29 L28 M27 M26 J29 J28 K27 K26 G29 G28 H27 H26 E29 E28 F27 F26 C29 C28 D27 D26 D23 D24 F23 D25 E23 N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3 AG2 AG1 PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP V27 V26 U29 U28 Y27 Y26 W29 W28 AB27 AB26 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 AF29 AF28 AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 CLK_PCIE_ICH# CLK_PCIE_ICH DMI_IRCOMP_R USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+ USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+ USBP6USBP6+ USBP7USBP7+ USBP8USBP8+ USBP9USBP9+ T533 T534 T530 T531 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
Description
INT VGA EXT VGA Internal TPM
6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
Direct Media Interface
IV@0.1u/10V_4 PCIE_TXN2_C IV@0.1u/10V_4 PCIE_TXP2_C
0.1u/10V_4 0.1u/10V_4
PCIE_TXN3_C PCIE_TXP3_C
IRDY# PAR PCIRST# DEVSEL# PERR# SERR# STOP# TRDY# FRAME#
PCI-Express
CBE0# CBE1# CBE2# CBE3#
PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
+1.5V_PCIE_ICH
EV@0.1u/10V_4 PCIE_TXN4_C EV@0.1u/10V_4 PCIE_TXP4_C
0.1u/10V_4 0.1u/10V_4
PCIE_TXN5_C PCIE_TXP5_C
DMI_