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淘豆网网友近日为您收集整理了关于电子论文-FlashFlex51_MCU_SST89C54_SST89C58的文档，希望对您的工作和学习有所帮助。以下是文档介绍：FlashFlex MCUSSTC / SSTCPreliminary Specifications
Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP and SoftLock are- / trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.FEATURES: Multi-Purpose -bit
patibleMicrocontroller Unit (MCU) with EmbeddedSuperFlash Memory Fully Software and Development patible as well as Pin-For-Pin patible with Standard xCxMicrocontrollers
Bytes Register/Data RAM / KByte Embedded High PerformanceFlexible SuperFlash EEPROM– One / KByte block (-Bytesector size)– One
KByte block (-Byte sector size)– Individual Block Security Lock with Softlockfeature– Cx patible– Concurrent Operation during In-ApplicationProgramming(IAP)– Memory Re-Mapping for Interrupt Supportduring IAP Support External Address Range up to KByte of Program and Data Memory High Current Drive on Port
(, , ) pins Three -bit Timer/Counter Programmable Serial Port (UART) Six Interrupt Sources at
Priority Levels Selectable Watchdog Timer (WDT) Four -bit I/O Ports ( I/O Pins) TTL- and patible Logic Levels Extended Power-Saving Modes– Idle Mode– Power Down Mode with External InterruptWake-up– Standby (Stop Clock) Mode High Speed Operation at
Volts ( to MHz) Low Voltage (.V) Operation ( to MHz) PDIP-, - and TQFP- Packages Temperature Ranges:– Commercial (°C to +°C)– Industrial (-°C to +°C)PRODUCT DESCRIPTIONSSTC and SSTC are members of theFlashFlex family of -bit microcontrollers. TheFlashFlex family is a family of embeddedmicrocontrollerproductsdesignedandmanufacturedonthe state-of-the-art SuperFlash CMOS semiconductorprocess technology.As a member of the FlashFlex controller family, theSSTC/ uses the same powerful instruction set,has the same architecture, and is pin-for-patiblewith standard xCx microcontroller devices.SSTC/es with / KByte ofintegrated on-chip flash EEPROM program memoryusing the patented and proprietary Silicon StorageTechnology, Inc. (SST) CMOS SuperFlash EEPROMtechnology with the SST field enhancing tunnelinginjector split-gate memory cells. The SuperFlashmemory is partitioned into
independent programmemory blocks. The primary SuperFlash Block
occu-pies / KByte of internal program memory space andthe secondary SuperFlash Block
KByte ofSSTC/’s internal program memory space. The KByte secondary SuperFlash block can be mapped tothe highest or lowest location of the
KB it can also be hidden from the program counterand used as an independent EEPROM-like datamemory. The flash memory blocks can be programmedvia a standard Cx OTP EPROM programmer fittedwith a special adapter and firmware for SSTC/devices. During the power-on reset, the SSTC/can be configured as a master for source code storageor as a slave to an external host for In-ApplicationProgramming (IAP) operation. SSTC/ is de-signed to be programmed “In-System” and “In-Applica-tion” on the printed circuit board for maximum flexibility.The device is pre-programmed with a sample bootstraploader in the memory (see Note ), demonstrating theinitial user program code loading or subsequent usercode updating via the “IAP” operation.In addition to / KByte of SuperFlash EEPROMprogram memory on-chip, the SSTC/ can ad-dress up to
KByte of program memory external to thechip. The SSTC/ have
bits of on-chipRAM. Up to
KByte of external data memory (RAM)can be addressed.Thehighlyreliable,patentedSuperFlashtechnologyandmemory cell architecture have a number of importantadvantages for designing and manufacturing flashEEPROMs, pared with other approaches.These advantages translate into significant cost andreliability benefits for our customers.Note : The sample bootstrap loader is for the user’s reference andconvenience only. SST does not guarantee the functionalityor the usefulness of the sample bootstrap loader. Chip-Eraseor Block-Erase operations will erase the pre-programmedsample code.
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsTABLE OF CONTENTSPRODUCT FEATURES ......................................................................................................................................... PRODUCT DESCRIPTION .................................................................................................................................... FUNCTIONAL BLOCKS ......................................................................................................................................... Functional Block Diagram ............................................................................................................................... PIN ASSIGNMENTS .............................................................................................................................................. Pin Descriptions .............................................................................................................................................. ANIZATION ................................................................................................................................... Program Memory ............................................................................................................................................ Memory Re-Mapping..................................................................................................................................... Activation and Deactivation of Memory Re-Mapping ............................................................................... Data Memory ................................................................................................................................................ Special Function Registers (SFR) ................................................................................................................. CPU Related SFRs.................................................................................................................................. Flash Memory Programming SFRs.......................................................................................................... Watchdog Timer SFRs ............................................................................................................................ Timer/Counters SFRs .............................................................................................................................. Interface SFRs......................................................................................................................................... FLASH MEMORY PROGRAMMING .................................................................................................................... External Host Programming Mode ................................................................................................................ Product Identification ............................................................................................................................... External Host mands .............................................................................................................. External Host Mode Clock Source ........................................................................................................... mand .................................................................................................................................... Programming a SSTC/ ................................................................................................................. Flash Operation Status Detection (Ext. Host Handshake) ....................................................................... In-Application Programming Mode ................................................................................................................ In-Application Programming Mode Clock Source..................................................................................... IAP Enable Bit ......................................................................................................................................... In-Application Programming mands........................................................................................ Polling ...................................................................................................................................................... Interrupt Temination................................................................................................................................. TIMERS/COUNTERS...........................................................................................................................................
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsSERIAL I/O (UART).............................................................................................................................................. WATCHDOG TIMER ............................................................................................................................................ SECURITY LOCK ................................................................................................................................................ Hard Lock................................................................................................................................................. SoftLock ................................................................................................................................................... Status of the Security Lock ........................................................................................................................... RESET ................................................................................................................................................................ Power-On Reset ........................................................................................................................................... POWER-SAVING MODES ................................................................................................................................... CLOCK INPUT OPTIONS .................................................................................................................................... ELECTRICAL SPECIFICATION ........................................................................................................................... Absolute Maximum Ratings .......................................................................................................................... Operation Range........................................................................................................................................... Reliability Characteristics .............................................................................................................................. DC Electrical Characteristics......................................................................................................................... AC Electrical Characteristics ......................................................................................................................... Explanation Of Symbols .......................................................................................................................... External Clock Drive ................................................................................................................................ Serial Port Timing - Shift Register Mode .................................................................................................. PRODUCT ORDERING INFORMATION ............................................................................................................. Part Number binations .................................................................................................................. PART NUMBER CROSS REFERENCE GUIDE .................................................................................................. PACKAGING DIAGRAMS ....................................................................................................................................
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsFUNCTIONAL BLOCK DIAGRAMFUNCTIONAL BLOCKSRSTVSSVDDALE/PROG#PSEN#EA#XTAL XTALSuperFlashEEPROMK x Program/Erase& IAPControlSuperFlash EEPROM/K x CPUPort I/OI/OI/OI/OPort Power ModeManagementBus ControllerTTTWDT-bitUARTRAM x InterruptControlSFRsSecurityLockModeControlOscillator&TimingPort Port
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsP.P.P.RST(RXD) P.NC(TXD) P.(INT#) P.(INT#) P.(T) P.(T) P.P. (AD)P. (AD)P. (AD)P. (AD)EA#NCALE/PROG#PSEN#P. (A)P. (A)P. (A)
P.P.P.P.(TEx)P.(T)NCVDDP.(AD)P.(AD)P.(AD)P.(AD)(WR#)P.(RD#)P.XTALXTALVSSNC(A)P.(A)P.(A)P.(A)P.(A)P.-Pin Top View ILL F.PIN ASSIGNMENTSFIGURE : PIN ASSIGNMENTS FOR -PIN PLASTIC DIPPI-PACKAGEFIGURE : PIN ASSIGNMENTS FOR -PIN TQFPTQJ-PACKAGENote: NC pins must be left unconnected.FIGURE : PIN ASSIGNMENTS FOR -PIN J-PACKAGE(T) P.(T Ex) P.P.P.P.P.P.P.RST(RXD) P.(TXD) P.(INT#) P.(INT#) P.(T) P.(T) P.(WR#) P.(RD#) P.XTALXTALVSSVDDP. (AD)P. (AD)P. (AD)P. (AD)P. (AD)P. (AD)P. (AD)P. (AD)EA#ALE/PROG#PSEN#P. (A)P. (A)P. (A)P. (A)P. (A)P. (A)P. (A)P. (A)-Pin PDIPTop View ILL F.
P.P.P.RST(RXD) P.NC(TXD) P.(INT#) P.(INT#) P.(T) P.(T) P.P. (AD)P. (AD)P. (AD)P. (AD)EA#NCALE/PROG#PSEN#P. (A)P. (A)P. (A)
P.P.P.P.(TEx)P.(T)NCVDDP.(AD)P.(AD)P.(AD)P.(AD)(WR#)P.(RD#)P.XTALXTALVSSNC(A)P.(A)P.(A)P.(A)P.(A)P.-Pin TQFPTop View ILL F.
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsTABLE : PIN DESCRIPTIONSSymbol Type Name and FunctionsP[:] I/O Port : Port
is an -bit open drain bi-directional I/O port. As an output port eachpin can sink several LS TTL inputs. Port
pins that have ’s written to themfloat, and in that state can be used as high-impedance inputs. Port
is also themultiplexed low-order address and data bus during accesses to externalmemory. In this application it uses strong internal pull-ups when transitioningto ’s. Port
also receives the code bytes during FLASH MEMORYprogramming, and outputs the code bytes during program verification. Externalpull-ups are required during program verification.P[:] I/O with internal Port : Port
is an -bit bi-directional I/O port with internal pull-ups. The Port pull-ups output buffers can drive LS TTL inputs. Port
pins that have ’s written to themare pulled high by the internal pull-ups, and in that state can be used asinputs. As inputs, Port
pins that are externally pulled low will source current(IIL, on the data sheet) because of the internal pull-ups. P(, , ) have highcurrent drive of mA. Port
also receives the low-order address bytes duringFLASH MEMORY programming and program verification.P[] I T: (external count input to Timer/Counter ), clock-outP[] I TEX: (Timer/Counter
capture/reload trigger and direction control)P[:] I/O with internal Port : Port
is an -bit bi-directional I/O port with internal pull-ups. Port
pinspull-ups that have ’s written to them are pulled high by the internal pull-ups, andin that state can be used as inputs. As inputs, Port
pins that are externallypulled low will source current (IIL, on the data sheet) because of the internalpull-ups. Port
sends the high-order address byte during fetches from externalProgram memory and during accesses to external Data Memory that use -bitaddress (MOVX@DPTR). In this application it uses strong internal pull-upswhen outputting ’s. During accesses to external Data Memory that use -bitaddresses (MOVX@Ri), Port
sends the contents of the P Special FunctionRegister. Port
also receives some control signals and a partial of high-orderaddress bits during FLASH MEMORY programming and program verification.P[:] I/O with internal Port : Port
is an -bit bidirectional I/O port with internal pull-ups. The Port pull-ups output buffers could drive LS TTL inputs. Port
pins that have ’s written to themare pulled high by the internal pull-ups, and in that state can be used as inputs.As inputs, Port
pins that are externally pulled low will source current (IIL, on thedata sheet) because of the pull-ups. Port
also serves the functions of variousspecial features of the FlashFlex Family. Port
also receives some controlsignals and a partial of high-order address bits during FLASH MEMORYprogramming and program verification.P[] I RXD: Serial input lineP[] O TXD: Serial output lineP[] I INT#: External Interrupt P[] I INT#: External Interrupt P[] I T: Timer
external inputP[] I T: Timer
external inputP[] O WR#: External Data Memory Write strobeP[] O RD#: External Data Memory Read strobe
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsPIN DESCRIPTIONS (CONTINUED)Symbol Type Name and FunctionsPSEN# O/I Program Store Enable: PSEN# is the Read strobe to External ProgramMemory. When the SSTC/ are executing from Internal ProgramMemory, PSEN# is inactive (high). When the device is executing code fromExternal Program Memory, PSEN# is activated twice each machine cycle,except that two PSEN# activations are skipped during each access to ExternalData Memory. While the RST input is continually held high (for more than tenmachine cycles), a forced high-to-low input transition on the PSEN# pin will bringthe device into the “External Host” mode for the internal flash memoryprogramming operation.RST I Reset: A high logic state on this pin for two machine cycles (at least
oscillatorperiods), while the oscillator is running resets the device. After a essful pleted, if the PSEN# pin is driven by an input force with a high-to-lowtransition while the RST input pin is continually held high, the device will enter the“External Host” mode for the internal flash memory programming operation,otherwise the device will enter the “Normal” operation mode.EA# I External Access Enable: EA# must be connected to VSS in order to enable theSSTC/ to fetch code from External Program Memory locations startingat h up to FFFFh. Note, however, that if the Security Lock is activated oneither block, the logic level at EA# is internally latched during reset. EA# must beconnected to VDD for internal program execution. The EA# pin can tolerate a highvoltage of V (see Electrical Specification).ALE/PROG# I/O Address Latch Enable: ALE is the output signal for latching the low byte of theaddress during accesses to external memory. This pin is also the programmingpulse input (PROG#).XTAL I Oscillator: Input and output to the inverting oscillator amplifier. XTAL is input toXTAL O internal clock generation circuits from an external clock source.VDD I Power Supply: Supply voltage during normal, Idle, Power Down, and StandbyMode operations.Vss I Ground: Circuit ground. (V reference) PGM T.Note:
) I = InputO = Output) It is not necessary to receive a V programming supply voltage during flash programming.
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary ANIZATIONThe SSTC/ have separate address spaces forprogram and data memory.Program MemoryThere are two internal flash memory blocks in theSSTC/. The primary flash memory Block
has/ KByte and occupies the address space h toFFFh/FFFh.ThesecondaryflashmemoryBlockhas KByte and occupies the address space Fh toFFFFh.The/anizedas/uniformsectorswithsectoraddressfromAtoA. Each sector contains
rows with row address fromAtoA.EachrowhasByteswithbyteaddressfromA to A.FIGURE : ANIZATIONThe K x secondary SuperFlash block anized as uniform sectors with sector address from A to A.Each sector contains
rows with row address from Ato A. Each row contains
Bytes with byte addressfromAtoA.anizationforSSTC/.When internal code operation is enabled (EA# = ), theprimary / KByte flash memory block is alwaysvisible to the program counter for code fetching. Figures and
show the program anizations for theSSTC/.When internal code operation is enabled (EA# = ), thesecondary
KByte flash memory block is selectivelyvisible for code fetching. The secondary block is essible through the SuperFlash mailbox registers:SFCM, SFCF, SFAL, SFAH, SFDT and SFST. When bit of the SuperFlash Configuration mailbox register(SFCF[]),SFRaddresslocationBh,isset,thesecond-ary
KByte block will be visible by program counter.FFFhFhhFFFhhBlock
(/ KByte) ILL F.Sector Sector Sector FhFhFFFFhFFChFFhBlock
( KByte)Primary SecondarySector Sector FhCC
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsFIGURE : SSTC PROGRAM ANIZATION ILL F. KByteEXTERNAL KByteEXTERNAL KByteINTERNAL(Block ) KByteEXTERNAL KByteINTERNAL(Block ) KByteINTERNAL(Block )EA# =
& SFCF[] =
& SFCF[] =
EA# = FFFFhEFFFhFhhhFFFhFFFFhhhFFFFhhFFFh
Silicon Storage Technology, Inc. - /FlashFlex MCUSSTC / SSTCPreliminary SpecificationsMemory Re-mappingThe SSTC/ memory re-mapping feature allowsusers to anize internal Flash memory sectors sothat interrupts may be serviced when Block
of theinternal Flash is being programmed. Since Block upies the low order program address space of the architecture where the interrupt vectors reside,those interrupt vectors will normally not be availablewhen Block
is being programmed.SSTC/ provides four options of Memory Re-mapping (Refer to Table ). When the lowest
KBytesare remapped, any program access within logical ad-dress range h – FFFh will have the
most signifi-cant address bits forced to “”, redirecting the access toFh – FFFFh. Note that the physical contents of there-mapped portion of Block
(i.e. physical locationsh – FFFh in the current example) will not essible. Block
will still also be accessible throughFh – FFFFh. Figures
show re-mappedprogram anization for the SSTC/.FIGURE : SSTC PROGRAM ANIZATION ILL F. KByteEXTERNAL KByteEXTERNAL KByteINTERNAL(Block ) KByteEXTERNAL KByteINTERNAL(Block ) KByteINTERNAL(Block )EA# =
& SFCF[] =
& SFCF[] =
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FlashFlex MCUSSTC / SSTCPreliminary Specifications
Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. FlashFlex, In-Application Programming, IAP and SoftLock are- / trademarks of Silicon Storage Technology, Inc. These specifica...
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